GAA FET Nanosheet Channel Structure for Higher On-Current
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Solution Overview
Problem
Current semiconductor devices, such as FinFETs and GAA FETs, face challenges in optimizing the driving electrical current due to limitations in the width and thickness of channel regions, which affect the on-current performance.
Innovation Solution
The development of semiconductor GAA FET devices with varying numbers of nano sheets or nano wires, along with a manufacturing method that adjusts the channel width and number of nano structures to enhance the on-current, involves forming fin structures, alternating semiconductor layers, and etching processes to create specific source/drain regions and inner spacers, allowing for controlled channel dimensions and increased on-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the channel region dimensions (fin height or nano sheet thickness) are increased to improve on-current, then the driving electrical current increases, but the device density and integration scale are reduced
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional structures (FinFETs with vertical fins and GAA FETs with stacked nano sheets). This dimensional change allows the channel to extend vertically, increasing the effective channel area and on-current without occupying more horizontal chip area, thus maintaining high device density while improving driving current capability
Solution Approach 2:
The gate structure completely surrounds the channel region in GAA FETs, with multiple nano sheets nested vertically within a single device footprint. This nesting approach maximizes the channel area within a compact vertical space, enabling high on-current while maintaining small device area for high density integration
2Power
If the number of nano sheets or wires is increased to improve on-current, then the driving electrical current increases, but the manufacturing precision and control of channel dimensions become more difficult
Solution Approach 1:
The patent employs preliminary patterning steps where sacrificial layers are first formed, followed by spacer formation that defines the final channel dimensions. This self-aligned approach ensures precise control of nano sheet thickness and spacing before the actual channel formation, enabling consistent manufacturing across multiple stacked layers
Solution Approach 2:
Spacer layers serve as intermediaries that transfer the pattern from sacrificial layers to the final channel structure. These spacers provide precise dimensional control and alignment for multiple nano sheets, enabling accurate reproduction of channel dimensions across many stacked layers without direct lithographic patterning of each interface
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space. After the source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer.