Gate-All-Around FET Channel Control via Nested Nanowire Structures
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Solution Overview
Problem
As semiconductor technology advances to sub-10-15 nm nodes, gate-all-around (GAA) FETs face challenges in achieving further improvements due to the incomplete control over the channel region, particularly the bottom side, leading to short-channel effects and performance limitations.
Innovation Solution
The manufacturing process involves forming stacked semiconductor layers over a substrate, creating fin structures, and using anchor structures to support nanowires, allowing for the formation of a self-assembled nested gate structure that enhances channel control and mobility by forming source/drain layers epitaxially around the channel region, with a sacrificial gate structure and subsequent gate dielectric and electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Fin FET structure is used with gate adjacent to three side surfaces, then manufacturing complexity is reduced compared to GAA, but gate control over the channel region is incomplete leaving the bottom part far from gate electrode
Solution Approach 1:
The gate electrode completely surrounds the channel region in a nested configuration, with the gate dielectric layer interposed between the gate electrode and channel. This nested arrangement ensures all surfaces of the channel are under gate control while maintaining manufacturing feasibility through sequential deposition processes.
Solution Approach 2:
The gate structure transitions from planar or partial surrounding to complete three-dimensional surrounding of the channel region. This dimensional enhancement allows the gate to control all surfaces of the channel including the bottom, achieving fuller depletion without significantly increasing manufacturing complexity.
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm nodes, then device density and performance are improved, but short-channel effects and performance limitations worsen
Solution Approach 1:
The complete surrounding gate structure creates a nested configuration where the gate electrode encloses the channel region on all sides. This geometric arrangement strengthens the electric field control over the channel, suppressing short-channel effects and enabling continued scaling to sub-10-15 nm nodes with improved device density and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables fuller depletion in the channel region, reducing short-channel effects and improving the sub-threshold current swing and drain-induced barrier lowering, thereby enhancing the performance of GAA FETs.
Implementation Method 1
Epitaxial source/drain structures are formed on the exposed first semiconductor layers in the source/drain regions
Data Source
AI summary
A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.