GAA FET Power Rail Layout for Higher Metal Track Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink, it becomes challenging to reduce their size while increasing the number of metal tracks, such as power rails and signal lines, due to limited space, which affects device density and complexity.
Innovation Solution
A method for manufacturing gate-all-around (GAA) FETs and stacked channel FETs involves forming fin structures with alternating semiconductor layers, patterning them into nanowires, and embedding power rails below the active region to accommodate additional signal lines, thereby increasing device density and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to sub 10-15 nm technology nodes, then device density is improved, but gate control over the channel region deteriorates
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional gate-all-around control, where the gate electrode completely surrounds the channel region in the vertical dimension. This dimensional change allows the gate to control the channel from all directions (top, bottom, and sides), providing superior electrostatic control at sub-10nm nodes while maintaining high device density.
Solution Approach 2:
The gate electrode is positioned to completely surround and enclose the channel region, creating a nested structure where the gate contains the channel on all sides. This nested configuration maximizes the gate's control authority over the channel electrons, ensuring reliable device operation at scaled dimensions.
2Device complexity
If the number of metal tracks is increased, then device complexity is improved, but available space deteriorates
Solution Approach 1:
The patent moves power rails from the horizontal plane to the vertical dimension by embedding them below the active region. This allows additional signal lines to be routed in the horizontal plane without interfering with power delivery, effectively increasing the number of metal tracks while preserving available space through three-dimensional layout optimization.
Solution Approach 2:
The patent separates power delivery functions from signal routing functions by placing power rails in a different spatial layer (below the active region) than signal lines. This segmentation allows independent optimization of both power distribution and signal interconnects, enabling higher device complexity without proportionally increasing space requirements.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.