GAA FET Gate Separation Wall for Denser Transistor Layouts
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Solution Overview
Problem
As semiconductor technology advances to sub-10-15 nm nodes, gate-all-around (GAA) FETs face challenges in further performance improvements due to scaling limitations, particularly in electrical and physical separation between adjacent transistors, affecting device density and performance.
Innovation Solution
A method of manufacturing GAA FETs involving the formation of fin structures with stacked semiconductor layers, sacrificial cladding layers, and gate dielectric layers to enhance electrical separation and reduce cell size, including the use of sacrificial gate electrodes and dielectric spacers to create a gate separation wall for improved transistor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to sub-10-15 nm nodes to increase device density, then device density is improved, but short-channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D gate control to three-dimensional gate-all-around structures that wrap around the channel region in multiple dimensions. This includes FinFET configurations where the gate surrounds three surfaces of the channel, and GAA FET configurations where the gate completely encircles the channel, providing control from top, bottom, and sidewalls. This dimensional evolution enables effective electrostatic control at ultra-scaled nodes by utilizing vertical and lateral dimensions simultaneously.
Solution Approach 2:
The gate structure is nested around the channel region in a concentric configuration, with the gate electrode completely surrounding the channel in GAA FETs. This nested arrangement allows the gate to control the channel from all directions, maximizing the control volume-to-surface area ratio and providing superior electrostatic control that suppresses short-channel effects while maintaining compact device footprint.
2Reliability
If gate structure wraps around fin on three surfaces to achieve better control, then gate control is improved, but manufacturing complexity worsens
Solution Approach 1:
The patent employs preliminary patterning actions where sacrificial layers are first formed and precisely patterned before the actual gate structure is built. These sacrificial structures serve as templates that guide subsequent material deposition and patterning steps, ensuring accurate alignment and geometry of the final gate-all-around structure. This preliminary structuring simplifies the overall manufacturing process by breaking down complex 3D formation into manageable sequential steps.
Solution Approach 2:
Sacrificial layers and mandrel structures are introduced as intermediary elements that facilitate the formation of complex gate-all-around structures. These temporary structures are deposited, patterned, and etched to create precise templates, which then guide the formation of the final gate electrode and dielectric layers. After the gate structure is successfully formed using these intermediaries, the sacrificial materials are removed, leaving the desired 3D gate configuration.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers is formed, an isolation insulating layer is formed so that the stacked layer are exposed from the isolation insulating layer, a sacrificial cladding layer is formed over at least sidewalls of the exposed stacked layer, a sacrificial gate electrode is formed over the exposed stacked layer, an interlayer dielectric layer is formed, the sacrificial gate electrode is partially recessed to leave a pillar of the remaining sacrificial gate electrode, the sacrificial cladding layer and the first semiconductor layers are removed, a gate dielectric layer wrapping around the second semiconductor layer and a gate electrode over the gate dielectric layer are formed, the pillar is removed, and one or more dielectric layers are formed in a gate space from which the pillar is removed.