GAA FET Isolation Layout for Sidewall Etching and Threshold Control
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Solution Overview
Problem
The existing methods for forming gate-all-around (GAA) field-effect transistors (FETs) face challenges in completely removing sacrificial non-channel layers due to limited exposure of sidewalls to etchants, which affects the formation of metal gate structures and threshold voltage control.
Innovation Solution
The method involves forming SiGe cladding layers of varying thicknesses and compositions between semiconductor fins to adjust the spacing between dielectric fins, ensuring complete removal of non-channel layers and improving the exposure of sidewalls during the etching process, thereby facilitating the formation of metal gate stacks with suitable threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form GAA FETs, then the process is simpler, but the non-channel layers cannot be completely removed due to insufficient sidewall exposure to etchant
Solution Approach 1:
The method performs preliminary actions by forming isolation structures and applying spacers to the semiconductor fins before the etching process. This preliminary structuring ensures that sidewalls are adequately exposed to the etchant, enabling complete removal of non-channel layers while maintaining a systematic and controlled process flow.
Solution Approach 2:
The patent introduces intermediary elements (isolation structures and spacers) that mediate between the semiconductor fins and the etchant. These intermediaries facilitate proper etchant access to sidewalls and enable complete non-channel layer removal without requiring direct complex manipulation of the fins themselves.
2Reliability
If sacrificial non-channel layers are not completely removed, then the process is simpler, but the subsequent formation of metal gate stack is negatively impacted
Solution Approach 1:
The isolation structures and spacers are formed in advance to prepare the structure for complete non-channel layer removal. This preliminary preparation ensures that when the etching process occurs, the sidewalls are properly exposed, leading to complete layer removal and enabling reliable subsequent metal gate stack formation.
Solution Approach 2:
The method applies preliminary anti-action by using isolation structures and spacers to prevent the problem of incomplete etching before it occurs. These structures pre-positioned on the fins ensure that etchant can access all necessary areas, counteracting the tendency for incomplete removal that would otherwise harm metal gate stack formation.
3Manufacturing precision
If sidewalls are not sufficiently exposed to etchant, then the structure remains simpler, but threshold voltage control is compromised
Solution Approach 1:
Spacers serve as intermediary elements that position isolation structures at precise locations relative to the semiconductor fins. This intermediary spacing mechanism ensures sufficient sidewall exposure to etchant for complete non-channel layer removal, thereby enabling precise threshold voltage control without requiring direct complex structuring of the fins.
Solution Approach 2:
The isolation structures are selectively positioned only at specific locations where sidewall exposure is needed, rather than uniformly across the entire device. This localized approach provides the necessary threshold voltage control through complete non-channel layer removal while minimizing overall structural complexity.
Data Source
AI summary
A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.