GAA FET Source/Drain SiGe Epitaxy for Lateral Etch Control
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Solution Overview
Problem
In semiconductor manufacturing, particularly for GAA FETs, controlling lateral etching during NW release is challenging due to insufficient etching control, leading to issues with gate-to-drain capacitance and the need for defect-free source/drain epitaxial layers.
Innovation Solution
A novel method for fabricating source/drain epitaxial layers involves forming fin structures, etching sacrificial layers, and using epitaxial growth to create layers with varying Ge content and boron doping, with specific etching and annealing processes to ensure precise control and quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used for NW release, then the etching process is simple, but lateral etching control is insufficient leading to gate-to-drain capacitance issues
Solution Approach 1:
The etching process is divided into multiple sequential steps with different etchants and conditions. First, a sacrificial layer is etched to create initial spaces, then nanowires are released through selective etching, and finally source/drain regions are formed through epitaxial growth. Each step targets specific regions with controlled etching parameters to achieve precise lateral control while managing overall process complexity.
Solution Approach 2:
A sacrificial layer is deposited and patterned before nanowire formation to predefine the etching regions. This preliminary structure guides subsequent etching steps, ensuring that lateral etching occurs only in desired areas. The sacrificial layer acts as a template that controls the spatial distribution of etching effects, achieving precision without requiring complex real-time control during etching.
2Reliability
If insufficient etching control is used, then the manufacturing process is simpler, but gate-to-drain capacitance increases affecting device performance
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the gate electrode and source/drain regions. This layer is deposited conformally and then selectively removed in source/drain regions through etching. The dielectric layer acts as a mediator that prevents direct capacitance coupling between gate and drain, while its selective removal allows proper electrical connection where needed. This approach provides reliable capacitance control without requiring extremely precise etching control throughout the entire structure.
3Manufacturing precision
If multiple epitaxial layers with varying Ge content are formed, then source/drain layer quality is improved, but the manufacturing process becomes more complex
Solution Approach 1:
Multiple epitaxial layers with different germanium content are grown sequentially to create a graded structure. The first layer has lower Ge content (e.g., 5-15%) to ensure good crystalline quality and lattice matching, while subsequent layers have progressively higher Ge content (e.g., 20-30%) to achieve desired electrical properties. Each layer is optimized for its specific function, with interface quality controlled by gradual composition transitions. This local quality optimization improves source/drain layer performance while managing process complexity through systematic composition grading rather than random variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances etching control, reduces gate-to-drain capacitance, and produces defect-free source/drain epitaxial layers, improving the performance and reliability of GAA FETs.
Implementation Method 1
a source/drain epitaxial layer is formed in the source/drain space
Implementation Method 2
with specific etching and annealing processes to ensure precise control and quality
Data Source
AI summary
A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.