GAA FET Source/Drain Spacer Structure for Leakage Isolation
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Solution Overview
Problem
Suppressing leakage current (off-current) is a key issue in advanced semiconductor devices, particularly in three-dimensional designs such as multi-gate field effect transistors like finFET and gate-all-around FETs.
Innovation Solution
The implementation of an advanced isolation structure below the source/drain epitaxial layer in semiconductor GAA FETs, involving the formation of fin structures, recessed source/drain spaces, and the use of epitaxial layers to enhance channel region isolation, along with the formation of a metal gate structure to wrap around semiconductor wires or sheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor designs are used, then manufacturing is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar two-dimensional transistor channels to three-dimensional vertical channel structures (finFETs and GAA FETs). The fin structure creates a vertical channel extending from the substrate surface downward, while GAA FETs implement channels extending in multiple directions around the gate, effectively utilizing the third dimension to increase channel area and device density without increasing footprint area.
Solution Approach 2:
The gate structure in GAA FETs completely surrounds the channel region in a nested configuration, with the gate electrode wrapping around the channel from all sides. This nested gate-all-around structure provides maximum gate control over the channel while maintaining a compact vertical footprint, enabling higher density integration.
2Reliability
If three-dimensional fin structures are implemented, then channel control is improved, but leakage current increases
Solution Approach 1:
The source and drain regions are segmented into discrete blocks separated by isolation structures (dummy gates or dielectric regions) along the vertical channel. This segmentation divides the continuous channel into isolated segments, preventing leakage current paths between source and drain while maintaining effective gate control over each channel segment. The isolation structures act as barriers that block parasitic current flow.
Solution Approach 2:
Isolation structures (dummy gates or dielectric materials) are introduced as intermediary elements between the source and drain regions. These intermediaries physically separate the source and drain, blocking direct leakage paths while allowing the gate to maintain control over the channel. The isolation structures mediate between the conflicting requirements of continuous channel control and leakage prevention.
3Object-generated harmful factors
If advanced isolation structures are added below source/drain epitaxial layers, then leakage current is reduced, but manufacturing complexity increases
Solution Approach 1:
Isolation structures (dummy gates or dielectric regions) are formed during the early stages of device fabrication, before source/drain epitaxial growth and subsequent processing steps. By establishing isolation barriers in advance, the patent prevents leakage current paths from forming during later high-temperature annealing and doping processes, eliminating the need for additional isolation steps after epitaxial growth.
Solution Approach 2:
The isolation structures are integrated into the existing fin formation and gate fabrication工艺流程, combining multiple functions into unified process steps. The same lithography and etching steps used to create fin structures also define isolation regions, and the same deposition processes used for gate formation also create isolation layers, reducing the total number of discrete manufacturing steps.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure, in which first and second semiconductor layers are alternately stacked over a substrate, is formed, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers are laterally etched in the source/drain space, a first insulating layer is formed on a sidewall of the source/drain space, the first insulating layer is partially etched, thereby forming a first bottom spacer at a bottom of the source/drain space, a second insulating layer is formed on the sidewall of the source/drain space, the second insulating layer is partially etched, thereby forming inner spacers on end faces of the first semiconductor layers and leaving a part of the second insulating layer as a second bottom spacer at the bottom of the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space.