GAA FET Gate Structure With Insulating Substrate Isolation
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Solution Overview
Problem
As semiconductor technology advances to nanometer nodes, three-dimensional designs like FinFET and GAA FET face challenges with the bottom part of the channel not under gate control, leading to leakage current and parasitic PN junctions, which affect the ION/IOFF ratio.
Innovation Solution
Incorporating an insulating layer between the bottommost gate structure and the underlying semiconductor substrate in a GAA FET, reducing leakage current and minimizing parasitic PN junctions by forming a gate structure that surrounds the channel region on all sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate structure surrounds the channel region on all sides (GAA FET), then fuller depletion and less short-channel effects are achieved, but device complexity increases
Solution Approach 1:
The gate structure is nested within a sacrificial mandrel structure during fabrication. The mandrel is formed first, then the gate is deposited around it, creating a nested configuration that simplifies the formation of the complex gate-all-around structure while achieving fuller depletion control
2Productivity
If transistor dimensions are scaled down, then device density increases, but leakage current and parasitic PN junctions worsen
Solution Approach 1:
A sacrificial mandrel structure is introduced as an intermediary element during fabrication. This mandrel serves as a template for forming the gate-all-around structure and helps control the formation of parasitic PN junctions at the bottom of the channel, thereby reducing leakage current while enabling continued scaling
Solution Approach 2:
The sacrificial mandrel is formed in advance to prevent the formation of parasitic PN junctions before they can cause leakage issues. By having the gate structure predetermined around the mandrel, the harmful parasitic junctions are avoided from the outset, enabling safer dimension scaling
Data Source
AI summary
An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substrate.