Multi-Layer GAA FET Channels for Simpler Threshold Voltage Tuning
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Solution Overview
Problem
The fabrication of gate-all-around (GAA) FETs with multi-layer channel regions is complex due to the challenge of tuning threshold voltage in metal gate structures, especially when dealing with nanoscopic features, as the process involves deposition and patterning of different work function metal layers, which becomes intricate at reduced length scales.
Innovation Solution
The method involves forming GAA CMOSFETs with channel regions configured using alternating silicon (Si) and silicon-germanium (SiGe) layers, allowing the threshold voltage of n-channel and p-channel FETs to be tuned using work function metal layers of the same composition, reducing processing complexity by selectively etching SiGe layers to form openings for metal gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If different work function metal layers are deposited and patterned to tune threshold voltage in GAA FETs with nanoscopic features, then threshold voltage tuning capability is improved, but processing complexity increases significantly
Solution Approach 1:
The patent applies local quality by using the same work function metal layer composition for both n-channel and p-channel FETs, but achieving different threshold voltages through local structural differences in the channel region (nanosheets vs. nanorods) and selective doping. This eliminates the need for different metal layers while maintaining threshold voltage tuning capability.
Solution Approach 2:
The patent implements universality by using a single work function metal layer composition to serve dual purposes: forming both n-channel and p-channel FETs with appropriate threshold voltages. The same metal layer is deposited across the entire structure, and its function is differentiated through subsequent selective processing and channel structure variations rather than through material composition changes.
2Manufacturing precision
If multiple different work function metal layers are used to form metal gate structures in GAA FETs, then threshold voltage control is improved, but fabrication process complexity increases
Solution Approach 1:
The patent merges the functions of multiple work function metal layers into a single metal layer by combining threshold voltage control functionality with channel structure engineering. Instead of separating these functions into different metal layers, the invention integrates them, using one metal layer whose effective work function is modulated by the underlying channel structure (nanosheets versus nanorods) and doping profiles.
Solution Approach 2:
The patent employs parameter changes by varying the physical and chemical parameters of the channel region (nanosheet thickness, nanorod diameter, doping concentration, oxide layer thickness) to achieve different effective work functions and threshold voltages from the same metal gate material. This allows continuous tuning of device characteristics without changing the metal layer composition.
3Area of stationary object
If nanoscopic features are closely arranged in vertical stacks to increase functional density, then IC chip footprint is reduced, but processing precision requirements increase
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar 2D channel structures to three-dimensional vertical channel structures (nanosheets and nanorods arranged in vertical stacks). This vertical stacking enables increased functional density and reduced chip footprint by utilizing the third dimension, while the self-aligned nature of the vertical growth process helps manage the increased precision requirements.
Solution Approach 2:
The patent implements the nested doll principle by creating hierarchical structures where nanosheets or nanorods are nested within gate structures, which are in turn nested within multi-layer dielectric and contact structures. This nested arrangement allows compact integration of multiple functional elements in a vertically stacked configuration, maximizing space utilization while maintaining manufacturability.
Data Source
AI summary
A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.