GAA FET Wire Connectivity via Etching Depth Control

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Solution Overview

Problem

Manufacturing gate-all-around (GAA) FETs with varying numbers of semiconductor wires within a single semiconductor chip is challenging due to difficulties in achieving precise control over the number of wires and their electrical connections, affecting driving current and input capacitance.

Innovation Solution

The method involves adjusting the number of semiconductor wires electrically connected to the source/drain epitaxial layer by varying the etching depth of the source/drain space, allowing for different numbers of wires to be in contact with the epitaxial layer, thereby modulating the driving current and reducing input capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the number of semiconductor wires is increased to improve driving current, then the driving current increases, but the input capacitance increases and device size increases

Engineering Contradiction:

Improvedriving currentVSAvoidinput capacitance

Core Design Contradiction:

PowerVSQuantity of substance

Solution Approach 1:

The patent applies dynamics by making the number of electrically connected semiconductor wires variable rather than fixed. By controlling etching depth, the same physical structure can dynamically adjust the number of active wires (e.g., 1, 2, 3, or 4 wires) to connect to the source/drain epitaxial layer, enabling flexible modulation of driving current and input capacitance based on operational requirements

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of wire connectivity by varying etching depth. This parameter change allows the system to transition between different operational states (different numbers of connected wires) without changing the physical layout, thereby adjusting driving current and input capacitance according to circuit needs

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If different configurations of GAA FETs are implemented on the same chip to improve versatility, then adaptability increases, but manufacturing complexity increases

Engineering Contradiction:

Improvedevice configuration flexibilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent achieves universality by creating a single manufacturing process that can produce multiple device configurations (different numbers of connected wires) from the same physical structure. The same fin structure with multiple semiconductor wires can serve different functions depending on etching depth, eliminating the need for separate manufacturing lines for different device types

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent applies local quality by creating spatial variation in wire connectivity through controlled etching. Different regions of the same fin structure can have different numbers of connected wires based on local etching depth, allowing heterogeneous device configurations across the chip while using uniform manufacturing processes

Inventive Principle:

Principle #3Local quality

3Manufacturing precision

If precise control over the number of wires and their electrical connections is achieved to improve manufacturing precision, then device performance control improves, but process difficulty increases

Engineering Contradiction:

Improvewire connection controlVSAvoidprocess difficulty

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent replaces complex mechanical or lithographic methods for controlling wire connectivity with a simpler chemical etching process. By using etching depth as the control mechanism, the system achieves precise wire connection control through a well-established semiconductor manufacturing technique rather than requiring new complex process equipment or methods

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables flexible adjustment of driving current and input capacitance, improving operational speed and reducing the size of semiconductor devices by allowing for different configurations of GAA FETs on the same chip.

Implementation Method 1

varying the etching depth of the source/drain space

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS11195763B2Method of manufacturing a semiconductor device and a semiconductor device

Publication Date: 2021.12.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.