GAA Fin Isolation Structure with Bilayer Liner Planarity Control
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Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) devices face challenges in avoiding concave surfaces of isolation structures, which can lead to defects in the GAA device during the scaling down process.
Innovation Solution
The formation of isolation structures with a bilayer liner scheme, where the liner layers have different etching rates, is employed to avoid concave surfaces by recessing the dielectric material and planarizing the top surfaces, ensuring the isolation structures are surrounded by fins with the fins rising above them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional single-layer liner isolation structures are used, then the manufacturing process is simple, but concave surfaces form on the isolation structures during etching, leading to device defects
Solution Approach 1:
The liner layer is segmented into multiple layers (first liner layer and second liner layer) with different etching rates. This segmentation allows the first liner layer to be selectively removed while the second liner layer remains, preventing concave surface formation and maintaining planarity without significantly complicating the manufacturing process.
2Manufacturing precision
If the dielectric material is recessed to avoid concave surfaces, then surface planarity is improved, but the etching process becomes more complex and time-consuming
Solution Approach 1:
The etching process parameters are changed by utilizing the different etching rates of the two liner layers. The first liner layer has a higher etching rate and is selectively removed, while the second liner layer with lower etching rate remains to maintain planarity. This parameter-based differentiation simplifies the overall etching process compared to multi-step recessing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents defects in GAA devices by maintaining a planar top surface and ensuring proper isolation, enhancing the manufacturing process and device integrity.
Implementation Method 1
etching the first liner layer, the second liner layer, and the dielectric material to form an isolation structure between the fins
Data Source
AI summary
A method for manufacturing a semiconductor structure includes forming fins over a substrate. The fins each includes first semiconductor layers and second semiconductor layers alternatingly stacked. The method further includes forming a first liner layer on sidewalls of the fins and over the substrate, forming a second liner layer having first dopants on sidewalls of the first liner layer and over the first liner layer, forming a dielectric material between sidewalls of the second liner layer, etching the first liner layer, the second liner layer, and the dielectric material to form an isolation structure between the fins, forming a cladding layer on sidewalls of the fins and over the isolation structure, forming source/drain features in the fins, removing the first semiconductor layers and the cladding layer to form gate trenches, and forming gate structures in the gate trenches and wrapping around the second semiconductor layers.