GAA Fin Structure With Connecting Layer for Clean Dummy Gate Removal
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Solution Overview
Problem
The existing technologies face challenges in forming semiconductor devices with a gate-all-around (GAA) structure due to difficulties in removing the dummy gate structure without residue and forming gate structure sidewall spacers, especially with shrinking spacings between fins, which affects the quality and performance of the final device.
Innovation Solution
A semiconductor device fabrication method involving the formation of connecting layers on the sidewalls and between fins to connect them into a single fin, facilitating easier removal of the dummy gate structure and improving the formation of gate structure sidewall spacers, thereby enhancing the quality of the final semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fins are discretely arranged on the substrate, then the gate structure can be formed across each fin, but the dummy gate structure formation becomes complex and difficult to remove without residue
Solution Approach 1:
Multiple discretely arranged fins are merged into a single connected fin structure by forming a connecting layer between adjacent fins. This merging allows the dummy gate structure to be formed as one continuous element rather than multiple separate elements, significantly simplifying the subsequent removal process and eliminating residue issues.
Solution Approach 2:
A connecting layer is introduced as an intermediary element between adjacent fins. This connecting layer serves as a bridge that physically connects the fins, enabling the dummy gate structure to span across what were originally discrete fins as a single continuous structure, thereby simplifying fabrication and removal.
2Productivity
If spacings between fins are reduced to increase device density, then more fins can be integrated, but the formation of gate structure sidewall spacers becomes more difficult
Solution Approach 1:
By merging multiple closely-spaced fins into a single connected fin structure through the connecting layer, the effective spacing that matters for sidewall spacer formation is increased. The sidewall spacers are formed on the outer sidewalls of the connected fin structure, and the internal spaces between originally discrete fins are filled by the connecting layer, eliminating the difficulty of forming spacers in narrow gaps.
3Productivity
If only regions close to the top surface and sidewalls of fins are used as channel regions, then the Fin FET structure is simpler, but the volume used as channel regions is small, restricting operating current
Solution Approach 1:
Multiple fins are merged into a connected fin structure, increasing the total volume available as channel region. The connecting layer provides additional channel volume between the originally discrete fins, thereby increasing the overall operating current capability while maintaining the Fin FET structural concept.
Solution Approach 2:
The channel region is extended into the horizontal dimension by forming a connecting layer between adjacent fins. This creates a three-dimensional channel structure where current can flow through multiple paths (through individual fins and through the connecting layer), effectively increasing the total channel volume and operating current.
Data Source
AI summary
A semiconductor device includes a substrate, a plurality of fins discretely arranged on the substrate, a connecting layer on sidewalls of the plurality of fins and between adjacent fins, and a gate structure across the plurality of fins and the connecting layer on the substrate. A top surface of the connecting layer is coplanar with a top surface of the plurality of fins. Each fin of the plurality of fins includes one or more channel layers spaced apart from each other. Each of the one or more channel layers is surrounded by the gate structure.