GAA Fin Structure Etching With Modulated Ge Sacrificial Layers
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Solution Overview
Problem
In the fabrication of gate-all-around (GAA) FETs, controlling lateral etching of nanowires and shaping inner spacers is challenging due to insufficient etching control, leading to issues with gate control capability and uniformity, particularly in sub-10-15 nm technology nodes, which affects device performance and circuit speed.
Innovation Solution
The use of modulated composition sacrificial semiconductor layers allows for controlled lateral etching and improved shape control of inner spacers, enhancing gate control capability by forming source/drain epitaxial layers with specific Ge concentrations and dielectric films to manage etching and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for nanowire lateral etching, then the etching process is simple, but the lateral etching control is insufficient leading to poor uniformity and shape control of inner spacers
Solution Approach 1:
The patent modifies etching parameters by introducing modulated composition sacrificial semiconductor layers with varying Ge concentrations. Different etch rates are achieved through composition modulation, enabling precise lateral etching control and uniform inner spacer formation without overly complicating the process
Solution Approach 2:
The sacrificial semiconductor layer is segmented into multiple layers with different Ge concentrations (e.g., first sacrificial layer with 0-10% Ge, second sacrificial layer with 10-30% Ge). This segmentation allows differential etching rates to be achieved, improving lateral etching control and inner spacer shape control
2Manufacturing precision
If modulated composition sacrificial semiconductor layers are used, then lateral etching control and inner spacer shape control are improved, but the manufacturing process becomes more complex
Solution Approach 1:
Different regions of the sacrificial semiconductor layer are assigned different Ge concentrations tailored to local requirements. The first sacrificial layer (0-10% Ge) provides a foundation while the second sacrificial layer (10-30% Ge) enables precise lateral etching control, achieving uniform inner spacer shapes through localized composition optimization
Solution Approach 2:
The patent employs composite sacrificial semiconductor structures combining multiple materials with different Ge concentrations. This composite approach enables differential etching rates within a single sacrificial layer system, improving manufacturing precision while managing process complexity through material composition rather than process steps
3Reliability
If Ge concentrations in source/drain epitaxial layers are optimized, then gate control capability is enhanced, but the deposition process requires more precise control
Solution Approach 1:
Modulated composition sacrificial semiconductor layers are prepared in advance with specific Ge concentrations before the epitaxial growth step. This preliminary composition design enables subsequent source/drain epitaxial layers to achieve optimal Ge concentrations (e.g., 20-40% Ge) for enhanced gate control, while the deposition process itself requires less precise control
4Stability of the object's composition
If inner spacers are formed with better shape control, then gate control uniformity from channel bottom to top is improved, but the overall device complexity increases
Solution Approach 1:
The patent achieves uniform gate control from channel bottom to top by modifying the composition parameters of sacrificial semiconductor layers. The modulated Ge concentrations (0-10% in first layer, 10-30% in second layer) enable uniform lateral etching and inner spacer formation, improving gate control uniformity without significantly increasing device structure complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity and effectiveness of gate control from the channel bottom to top, reducing channel resistance and enhancing the performance of GAA FETs, particularly on 12-inch wafers, by managing the composition of sacrificial layers and inner spacers.
Implementation Method 1
a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space
Implementation Method 2
a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer
Data Source
AI summary
In a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. In etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed.