Fin Isolation Region Layout for Low-Capacitance GAA Gate Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of Integrated Circuit (IC) technology has increased the complexity of processing and manufacturing, particularly in the formation of Gate-All-Around (GAA) transistors, where the formation of isolation regions like Continuous Polysilicon on Diffusion edge (CPODE) regions poses challenges due to the need for wider photoresist strips to prevent collapse and reduce defect rates.
Innovation Solution
The formation of CPODE isolation regions on neighboring gate stacks with overlaps in the gate length direction results in wider photoresist strips, reducing the likelihood of photoresist collapse and defect rates during the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If photoresist strips are made wider to prevent collapse during patterning, then photoresist structural stability is improved, but the manufacturing precision of isolation region formation deteriorates due to increased overlap and difficulty in controlling exact dimensions
Solution Approach 1:
The patent divides the isolation region formation into multiple etching steps with different photoresist patterns. Instead of using a single wide photoresist strip, the process segments the formation into sequential steps where each step uses appropriately sized photoresist strips, thereby maintaining photoresist stability while achieving precise isolation region dimensions through cumulative patterning
Solution Approach 2:
The patent performs preliminary patterning actions to define the isolation region boundaries before final etching. By pre-establishing the pattern geometry in earlier process steps with controlled photoresist application, the subsequent etching steps can proceed with standard-width photoresist strips, avoiding the need for wider strips while maintaining structural stability and precision
2Reliability
If photoresist strips are made wider to reduce defect rates, then manufacturing reliability is improved, but the complexity of the patterning process increases due to additional overlap management
Solution Approach 1:
The patent segments the patterning process into multiple controlled etching steps, each with its own photoresist application and removal cycle. This segmentation allows each step to use standard-width photoresist strips with well-established handling procedures, reducing the overall process complexity compared to managing single wide strips with overlap requirements
Solution Approach 2:
The patent applies photoresist strips with intentional partial overlap in sequential steps, where the overlap region is deliberately used to ensure complete coverage and defect reduction. This partial excessive action (using overlap beyond minimum requirements) improves reliability while keeping individual photoresist strips at manageable widths, avoiding the complexity of managing very wide single strips
3Productivity
If scaling down continues to increase functional density, then production efficiency is improved, but the difficulty of processing and manufacturing increases
Solution Approach 1:
The patent segments the isolation region formation into multiple standardized etching steps that can be integrated into existing manufacturing workflows. By breaking down the complex scaling challenge into repeatable, modular process steps with standard photoresist dimensions, the difficulty of processing scaled devices is reduced while maintaining high functional density and production efficiency
Solution Approach 2:
The patent adjusts process parameters such as etching depth, photoresist strip width, and etching selectivity to accommodate scaled dimensions. By optimizing these parameters for each etching step rather than attempting to process all features at once, the patent enables continued scaling to increase functional density while managing processing difficulty through parameter control
Data Source
AI summary
A structure includes a plurality of semiconductor regions, a first gate stack and a second gate stack immediately neighboring each other, a first fin isolation region in the first gate stack, and a second fin isolation region in the second gate stack. The first fin isolation region and the second fin isolation region have a sideway overlap having an overlap distance being equal to or greater than a pitch of the plurality of semiconductor regions. The overlap distance is measured in a direction parallel to lengthwise directions of the first gate stack and the second gate stack. A plurality of source/drain regions are on opposing sides of the first gate stack and the second gate stack to form a plurality of transistors.