GAA Fin Structure Junction Profiling for Ultra-Low-Vt PMOS
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Solution Overview
Problem
The integration of gate-all-around (GAA) devices in semiconductor manufacturing is challenging due to complexity in fabricating the GAA features around nanowires, necessitating improved methods for forming semiconductor structures with different junction profiles to enhance gate control and reduce short-channel effects.
Innovation Solution
A method involving epitaxial proximity push processes is selectively applied to p-type transistors with ultra-low threshold voltage, while other p-type and n-type transistors are exempt, to adjust source/drain junctions and improve on-state current without compromising power savings, using photolithography and etching techniques to form nanostructures with varying threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GAA devices are integrated to improve gate control and reduce short-channel effects, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into distinct regions with different junction profiles. First p-type transistors are formed with a first junction profile while second p-type transistors are formed with a second junction profile, allowing differentiated treatment of different device regions to achieve optimal gate control for each type while managing manufacturing complexity through systematic segmentation
Solution Approach 2:
The patent applies different junction profiles to different transistor types within the same semiconductor structure. First p-type transistors receive a first junction profile optimized for their specific requirements, while second p-type transistors receive a second junction profile, enabling localized optimization of device performance without requiring complete redesign of the entire manufacturing process
2Power
If epitaxial proximity push process is applied to adjust source/drain junctions, then on-state current is improved, but power efficiency may be compromised
Solution Approach 1:
The epitaxial proximity push process is selectively applied only to first p-type transistors that require enhanced on-state current, while second p-type transistors are formed without this process to maintain power efficiency. This localized application of the proximity push process allows optimization of on-state current where needed without compromising power efficiency in devices where it is not required
Solution Approach 2:
The patent segments the transistor population into different categories based on their electrical requirements. First p-type transistors are processed with the epitaxial proximity push to achieve higher on-state current, while second p-type transistors are processed differently to maintain lower power consumption, allowing the system to optimize for different performance characteristics in different device regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances on-state current in p-type transistors with ultra-low threshold voltage while maintaining power efficiency, addressing the integration challenges of GAA devices and reducing short-channel effects.
Implementation Method 1
An etching process is performed to laterally recess the second semiconductor layers of the first fin structure to form first notches. A first patterned mask layer is formed to cover the second p-type device region. A first epitaxial process is performed to form a first n-type source/drain feature in the first recess and the first notches.
Implementation Method 2
The stack is patterned to form a first fin structure, a second fin structure and a third fin structure
Implementation Method 3
An etching process is performed to laterally recess the second semiconductor layers of the first fin structure to form first notches
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes forming a first fin structure in a first p-type device region and a second fin structure in a second p-type device region. Each of the first fin structure and the second fin structure includes alternatingly stacking first semiconductor layers and second semiconductor layers. The method also includes etching the first fin structure and the second fin structure to form a first recess and a second recess, respectively, forming a first patterned mask layer to cover the second p-type device region, laterally recessing the second semiconductor layers of the first fin structure to form first notches, removing the first patterned mask layer, forming a first p-type source/drain feature in the first recess and the notches, and forming a second p-type source/drain feature in the second recess.