GAA Semiconductor Fin Structure With SiGe Surface Passivation
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor features around silicon nanowires in semiconductor manufacturing is challenging due to the complexity of scaling down while maintaining gate control and mitigating short-channel effects.
Innovation Solution
The formation of passivation layers on exposed etched surfaces of SiGe layers using radicals or silicon deposition to cover dangling bonds, thereby reducing interface trap density and improving carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional processes are used to fabricate GAA features around silicon nanowires, then manufacturing simplicity is maintained, but gate control and short-channel effects cannot be effectively managed
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial nanowire structure and epitaxial layers before creating the gate structure. The gate-all-around features are then formed by removing the sacrificial nanowire and filling the resulting space, allowing the gate to surround the channel region on multiple sides for improved control while managing fabrication complexity through pre-planned structural preparation
Solution Approach 2:
The patent implements the nested doll principle by creating a gate structure that completely surrounds the channel region, with the gate wrapping around the channel on three sides and extending over the top. This nested configuration allows the gate to control the channel from multiple directions, significantly improving gate control and mitigating short-channel effects
2Productivity
If minimum feature size is scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor structure into distinct functional layers including sacrificial nanowire, first and second epitaxial layers, gate structure, and interlayer dielectric. This segmentation allows each component to be optimized and fabricated independently, enabling scaling to smaller dimensions while managing process complexity through modular fabrication steps
Solution Approach 2:
The patent utilizes parameter changes by varying the composition of epitaxial layers (e.g., SiGe vs. silicon), adjusting material properties such as etch selectivity and lattice matching. These parameter changes enable precise control over fabrication processes at scaled dimensions, improving productivity while maintaining manufacturability through material property optimization
3Reliability
If passivation layers are formed on exposed etched surfaces to reduce interface trap density, then carrier mobility improves, but manufacturing steps increase
Solution Approach 1:
The patent applies preliminary action by forming passivation layers on exposed etched surfaces of the sacrificial nanowire and epitaxial layers before completing the gate structure fabrication. This early passivation prevents interface trap formation that would degrade carrier mobility, while integrating the passivation step into the existing fabrication sequence to minimize additional process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively mitigates oxide formation, reduces interface trap density, and enhances carrier mobility, leading to improved performance of the resulting semiconductor device.
Implementation Method 1
The formation of passivation layers on exposed etched surfaces of SiGe layers using radicals or silicon deposition to cover dangling bonds
Implementation Method 2
The formation of passivation layers on exposed etched surfaces of SiGe layers using radicals or silicon deposition
Implementation Method 3
The formation of passivation layers on exposed etched surfaces of SiGe layers using radicals
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.