GAA and FinFET Co-Fabrication Using a Shared Layer Stack
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Solution Overview
Problem
Conventional methods for fabricating gate-all-around (GAA) transistors and FinFETs on the same substrate are costly and involve additional steps due to the formation of different epitaxial layer regions, which increases cost and reduces yield.
Innovation Solution
A method is developed to fabricate GAA transistors and FinFETs on the same substrate without forming different epitaxial layer regions, using a stack of alternating semiconductor and sacrificial layers, followed by selective removal and epitaxial deposition to form channel members, allowing simultaneous fabrication of both device types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If different epitaxial layer regions are formed to fabricate GAA transistors and FinFETs separately, then device fabrication is enabled, but manufacturing cost increases and yield decreases
Solution Approach 1:
The patent combines the fabrication processes for GAA transistors and FinFETs into a single unified process. By forming a common substrate with alternating semiconductor and sacrificial layers, both device types can be manufactured simultaneously in different regions of the same substrate, eliminating the need for separate epitaxial layer formations and reducing overall manufacturing complexity and cost.
Solution Approach 2:
The substrate structure is designed to serve multiple functions: it can form both GAA transistors in first regions and FinFETs in second regions using the same initial epitaxial layers. The alternating semiconductor and sacrificial layer configuration allows the same substrate to be processed differently in different regions to produce two distinct device types, achieving multi-functionality from a single fabrication approach.
2Reliability
If different epitaxial layer arrangements are used for GAA and FinFET fabrication, then device-specific performance is optimized, but process complexity and cost increase
Solution Approach 1:
The patent applies local quality by allowing different processing steps to be applied to different regions of the same substrate. While the initial epitaxial layer formation is uniform across the substrate, subsequent processing can be selectively applied to first regions (for GAA transistors) and second regions (for FinFETs), enabling each device type to receive optimized local treatment while sharing the common substrate foundation.
Solution Approach 2:
The substrate is segmented into different functional regions: first regions for GAA transistor fabrication and second regions for FinFET fabrication. This segmentation allows the same initial structure to be divided into zones that receive different subsequent processing, enabling both device types to achieve their specific performance requirements through region-specific optimization while maintaining a unified starting point.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs and improves yield by enabling the simultaneous production of GAA transistors and FinFETs on a single substrate, leveraging the advantages of both device types without the need for additional epitaxial layer formations.
Implementation Method 1
forming on a substrate a stack comprising a plurality of semiconductor layers interleaved by a plurality of sacrificial layers
Implementation Method 2
selectively removing the plurality of sacrificial layers to release a plurality of channel members
Data Source
AI summary
A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.


