GAA Fin Layout With Inactive Edge Fins for Iso-Dense Loading
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Solution Overview
Problem
The semiconductor industry faces challenges in forming gate-all-around (GAA) field-effect-transistor (FET) devices due to the iso-dense loading effect, which causes imbalanced processing conditions and poorly formed metal gate structures, especially on the edges of fin groups, leading to performance issues.
Innovation Solution
Incorporating inactive fins on the edges of adjacent fin groups, coupled with dielectric trenches, to mitigate the iso-dense loading effect by delaying the formation of inactive fins until after the dummy gate structure is defined, allowing for a well-defined metal gate profile and enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If inactive fins are formed early in the process, then the iso-dense loading effect is reduced, but the metal gate profile becomes poorly defined
Solution Approach 1:
The patent applies preliminary action by forming the inactive fins at a specific intermediate stage in the manufacturing process - after the dummy gate structure is defined but before the metal gate structure is formed. This timing allows the inactive fins to be in place to counteract the iso-dense loading effect during metal gate formation, while not interfering with the earlier definition of the dummy gate structure that establishes the metal gate profile.
2Stability of the object's composition
If inactive fins are formed to mitigate iso-dense loading effect, then processing balance is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by forming inactive fins specifically at the edge regions of adjacent fin groups, where the iso-dense loading effect is most pronounced. The inactive fins have the same structural characteristics as active fins but are positioned in locations where they provide balancing processing conditions without contributing to device functionality. This localized approach addresses the processing imbalance only where needed, rather than requiring changes to the entire fin structure.
Data Source
AI summary
A method for making a semiconductor device includes: forming a first through sixth fin structures over a substrate, all extending along a first lateral direction, the second fin structure separated from each of the first and third fin structures with a first distance, the fifth fin structure separated from each of the fourth and sixth fin structures with the first distance, and the third fin structure separated from the fourth fin structure with a second distance; forming gate structures overlaying a respective portion of each of the first through sixth fin structures; forming a first through sixth pairs of trenches by removing respective portions of each of the first through sixth fin structures not overlaid by the gate structures; forming a dielectric passivation layer over the third and fourth pairs of trenches; and growing source/drain structures in the first, second, fifth, and sixth pairs of trenches, respectively.