Hybrid Nanostructure GAA Fins With Sub-10 Nm Spacing Control
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Solution Overview
Problem
The fabrication of FinFET devices with gate-all-around (GAA) structures faces challenges in achieving precise control over the space between channel fins, which affects the threshold voltage and the ease of gate structure formation, particularly in reducing the fin-to-fin space to below 10 nm and ensuring efficient gate filling.
Innovation Solution
The method involves forming a disposable mandrel fin on a semiconductor substrate, growing epitaxial channel fins on its sidewalls, removing the mandrel fin to create a flexible space, and forming a gate structure that wraps around the channel fins, allowing for flexible control of the fin-to-fin space and easy gate filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional FinFET fabrication methods are used, then the gate structure formation is difficult and fin-to-fin space control is imprecise, but the manufacturing process is simpler
Solution Approach 1:
The patent applies preliminary action by forming the gate structure before the channel fins in a gate-first approach. The gate is formed as an initial structure, then channel fins are grown on its sidewalls using epitaxial growth. This preliminary formation of the gate enables precise control of fin-to-fin spacing while simplifying the overall manufacturing process, as the gate serves as a template for subsequent fin formation.
Solution Approach 2:
The patent uses an intermediary sacrificial layer (such as silicon dioxide or silicon nitride) deposited on the gate structure before epitaxial growth. This sacrificial layer acts as a mediator that enables selective growth of channel fins on the gate sidewalls and facilitates precise spacing control. The sacrificial layer is later removed to complete the gate-all-around structure.
2Productivity
If the fin-to-fin space is reduced to below 10 nm, then the device density increases, but the gate filling becomes more difficult
Solution Approach 1:
The gate-first approach performs the gate formation action before fin formation, allowing the gate structure to be established with precise dimensions. This preliminary action enables subsequent epitaxial growth of fins with controlled spacing below 10 nm, while the gate filling is already completed and does not require navigating narrow spaces.
Solution Approach 2:
The patent inverts the conventional sequence by forming the gate structure before the channel fins, rather than forming fins first and then filling the gate. This inversion of the manufacturing sequence makes gate filling trivial since the gate is already formed, while enabling precise sub-10 nm fin spacing through controlled epitaxial growth on the gate sidewalls.
3Reliability
If the gate structure wraps around the channel fins, then the transistor performance improves, but the fabrication complexity increases
Solution Approach 1:
The gate structure is formed preliminarily before the channel fins, providing a ready-made template for the gate-all-around structure. Channel fins are then grown epitaxially on the gate sidewalls, naturally forming the wrapping configuration. This preliminary gate formation simplifies the fabrication process while achieving the desired wrapped gate structure for improved transistor performance.
Solution Approach 2:
The gate structure serves itself as a template and guide for the formation of channel fins. By forming the gate first, it automatically defines the position, spacing, and geometry of the subsequent fin structures through epitaxial growth. This self-service approach eliminates the need for complex alignment and patterning steps, reducing fabrication complexity while achieving wrapped gate configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible control of the threshold voltage and simplifies the formation of GAA structures, allowing for smaller fin-to-fin spaces and improved gate filling, making the process easier than conventional methods and suitable for multiple technology nodes, including N16, N10, N7, N5, and beyond.
Implementation Method 1
growing epitaxial channel fins on its sidewalls
Data Source
AI summary
Semiconductor structures and methods for forming the same are provided. The semiconductor device includes a fin protruding from a substrate and an isolation structure surrounding the fin. The semiconductor device also includes a first channel layer and a second channel layer formed over the fin and at least partially overlapping the isolation structure. The semiconductor device further includes a gate structure formed in a space between the first channel layer and the second channel layer and wrapping around the first channel layer and the second channel layer.