Fluorine Drive-In for GAA Gate Dielectrics With Less Oxide Damage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in optimizing the performance of gate-all-around (GAA) transistors, particularly in adjusting the distribution of fluorine in gate dielectrics to enhance transistor performance.

Innovation Solution

A method is introduced to incorporate fluorine into the gate dielectrics of GAA transistors by forming semiconductor nanostructures, depositing a fluorine-containing layer, and adjusting the distribution of fluorine through a drive-in process, using diffusion liners with tailored profiles to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fluorine is incorporated into gate dielectrics to enhance transistor performance, then device efficiency is improved, but gate oxide damage may occur

Engineering Contradiction:
Improvetransistor performanceVSAvoidgate oxide damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A fluorine-containing layer is deposited on the gate dielectric before subsequent processing steps. This preliminary fluorine incorporation protects the gate oxide during later manufacturing processes while providing performance enhancement benefits.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The fluorine-containing layer acts as an intermediary between the gate dielectric and other materials/processes. It mediates the interaction by providing fluorine atoms that passivate the gate oxide surface, reducing damage from subsequent processing while maintaining electrical performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated, but additional problems arise in optimizing transistor performance

Engineering Contradiction:
Improveintegration densityVSAvoidtransistor performance optimization
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The fluorine-containing layer is applied selectively to the gate dielectric surface in the miniaturized transistor structure. This local treatment addresses performance optimization needs specifically at the gate interface, enabling reliable operation despite reduced feature sizes and increased integration density.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method allows for improved adjustment of transistor performance by controlling the fluorine distribution in gate dielectrics, reducing gate oxide damage and enhancing device efficiency.

Implementation Method 1

performing a drive-in process to drive fluorine in the fluorine-containing layer into the gate dielectric

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

depositing a fluorine-containing layer on the gate dielectric

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 3

depositing a fluorine-containing layer on the gate dielectric

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS20260059800A1Fluorine incorporation for GAA transistors and the structures thereof
Publication Date: 2026.02.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260059800A1 patent drawing
  • US20260059800A1 patent drawing
  • US20260059800A1 patent drawing

AI summary

A method includes removing a dummy gate stack to form a trench between gate spacers, and removing a sacrificial layer contacting a semiconductor region. The sacrificial layer and the semiconductor region are in the trench. The method further includes depositing a gate dielectric into the trench and on the semiconductor region, depositing a liner on the gate dielectric, depositing a fluorine-containing layer over the liner, performing a drive-in process to drive fluorine in the fluorine-containing layer into the gate dielectric, and depositing a conductive layer over the gate dielectric.