GAA Gate Structure With Asymmetric Channels for Easier Patterning
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Solution Overview
Problem
The challenge in manufacturing small GAA devices is the difficulty in filling high-k metal gates in the vertically shrinking space between channels, requiring stringent process control for patterning, which is not adequately addressed by existing semiconductor device fabrication methods.
Innovation Solution
A method that involves forming GAA transistors with increased channel widths from the bottom to the top, controlling the horizontal distance between the topmost channel and a nearby dummy fin to be less than twice the thickness of a hard mask layer, allowing the hard mask layer to be deposited only at the top of the topmost channel and between it and the dummy fin, thereby simplifying the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the vertical space between channels is reduced to make smaller GAA devices, then device density and integration are improved, but the difficulty of filling high-k metal gates and controlling patterning increases significantly
Solution Approach 1:
The patent applies asymmetry by making the channel widths non-uniform across the vertical stack, with wider channels at the bottom and narrower channels at the top. This asymmetric configuration creates sufficient horizontal spacing between adjacent channels in the vertical region, enabling proper deposition and patterning of high-k metal gate layers while maintaining high device density in smaller footprint areas.
Solution Approach 2:
The patent transitions from uniform lateral spacing to vertical dimensional variation by adjusting channel widths at different heights. This dimensional change in the vertical direction creates the necessary lateral clearance between channels for gate patterning processes, effectively solving the filling difficulty without compromising the overall device miniaturization.
2Manufacturing precision
If stringent process control is implemented for patterning high-k metal gates in tightly spaced channels, then manufacturing precision is improved, but device complexity and process difficulty increase
Solution Approach 1:
The patent implements preliminary action by pre-configuring the channel widths with an asymmetric profile before the high-k metal gate deposition process. This preparatory structural arrangement ensures that adequate spacing exists between channels from the outset, eliminating the need for complex in-process adjustments or stringent control measures during subsequent patterning operations.
Solution Approach 2:
The patent changes the geometric parameter of channel width distribution from uniform to asymmetric (wider at bottom, narrower at top). This parameter modification fundamentally alters the spatial relationships between channels, creating inherent clearance that simplifies the patterning process and reduces the stringency of process control requirements for high-k metal gate deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for stringent process control, making the patterning of high-k metal gates easier and more efficient, avoiding the complexities and defects associated with tighter process control in existing methods.
Implementation Method 1
depositing a hard mask layer
Implementation Method 2
depositing a hard mask layer
Data Source
AI summary
A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.