GAA Transistor Gate Stack Blocking Layer Against Oxygen Migration
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Solution Overview
Problem
The challenge in forming gate structures for nanostructure transistors, such as GAA FET devices, lies in the difficulty of wrapping a gate around each nanostructure due to small spacing, leading to oxygen migration, interfacial layer defects, and increased leakage currents, complicating the process.
Innovation Solution
A method involving the formation of a blocking layer over the interfacial layer using a thermally stable high-k material, followed by the deposition of high-k layers and a work function metal layer to form a metal gate, which addresses the issues of oxygen migration and defect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between nanostructures is reduced to increase integration density, then more components can be integrated into a given area, but oxygen migration into the interfacial layer increases causing defects and leakage currents
Solution Approach 1:
A blocking layer is introduced as an intermediary between the interfacial layer and the high-k dielectric layer. This blocking layer acts as a mediator that prevents oxygen from migrating into the interfacial layer during the formation and annealing of the gate structure, thereby eliminating the root cause of defects and leakage currents while enabling reduced nanostructure spacing for higher integration density
Solution Approach 2:
The blocking layer is formed in advance before depositing the high-k dielectric layer and performing annealing processes. This preliminary action prepares the structure by establishing a protective barrier that prevents oxygen migration during subsequent processing steps, allowing the gate structure to be formed without defects even when nanostructures are closely spaced
2Reliability
If a gate structure is formed to wrap around each nanostructure, then transistor performance is improved, but the process becomes complicated due to small spacing between nanostructures
Solution Approach 1:
The blocking layer is deposited beforehand to establish a protective barrier that prevents oxygen migration during subsequent high-k dielectric deposition and annealing processes. This preliminary preparation enables the gate structure to be formed without defects, simplifying the overall process while maintaining high transistor performance
Solution Approach 2:
The blocking layer serves as an intermediary that facilitates the formation of a high-quality gate structure by preventing oxygen migration during processing. This intermediary layer enables the wrap-around gate configuration to be achieved reliably without complicating the fabrication process, as the blocking layer passivates the interface and prevents defect formation
3Manufacturing precision
If the interfacial layer thickness is reduced to decrease capacitive-equivalent-thickness, then device performance is improved, but leakage currents increase due to oxygen migration and defects
Solution Approach 1:
The blocking layer acts as an intermediary barrier that prevents oxygen from migrating into the thin interfacial layer during gate structure formation and annealing. This protective blocking layer enables the interfacial layer to be made thinner for reduced capacitive-equivalent-thickness without suffering from oxygen-induced defects that would otherwise cause leakage currents
Solution Approach 2:
The blocking layer extracts or removes the harmful oxygen migration pathway by providing an alternative barrier. By introducing this blocking layer, oxygen is prevented from reaching the interfacial layer, thereby eliminating the source of defects and leakage currents that would otherwise accompany thin interfacial layer designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of the gate structure, reducing capacitive-equivalent-thickness and minimizing leakage currents while maintaining the integrity of the nanostructure transistors.
Implementation Method 1
a blocking layer is formed over the interfacial layer... performing a first annealing process to densify the dielectric interfacial layer
Implementation Method 2
performing a first annealing process to densify the dielectric interfacial layer
Implementation Method 3
overlaying the blocking layer with a first high-k dielectric layer... overlaying the first high-k dielectric layer with a second high-k dielectric layer
Data Source
AI summary
A method for fabricating a semiconductor device includes exposing one or more surfaces of a conduction channel of a transistor; overlaying the one or more surfaces with a dielectric interfacial layer; overlaying the dielectric interfacial layer with a blocking layer;performing a first annealing process to densify the dielectric interfacial layer; overlaying the blocking layer with a first high-k dielectric layer; forming one or more threshold voltage modulation layers over the first high-k dielectric layer; performing a second annealing process to adjust a doping profile of the first high-k dielectric layer; and overlaying the first high-k dielectric layer with a second high-k dielectric layer.