GAA Transistor Gate Structure With Cladding for Epitaxial Contact
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Solution Overview
Problem
Existing technologies for making gate-all-around (GAA) transistors face challenges in epitaxially growing a source/drain structure due to limited contact area, especially as channel layer dimensions shrink, leading to performance issues.
Innovation Solution
The solution involves forming a semiconductor cladding layer that extends along the cut edge of a stack of channel layers, allowing for the formation of a dummy gate structure over this cladding layer. This configuration creates a source/drain recess with asymmetric sidewalls, significantly increasing the contact area for epitaxial growth of the source/drain structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel layer dimensions are reduced to increase integration density, then more components can be integrated into a given area, but the contact area for epitaxial growth of source/drain structure becomes limited
Solution Approach 1:
The patent introduces a semiconductor cladding layer that extends laterally beyond the channel layers in the horizontal plane, transforming the contact geometry from a limited top-surface interaction to an extended lateral interaction. This dimensional extension provides additional epitaxial growth area without increasing the vertical footprint, thereby maintaining integration density while solving the contact area limitation.
Solution Approach 2:
The source/drain structure is segmented into multiple epitaxial growth regions: growth on the channel layers themselves and separate growth on the extended semiconductor cladding layer. This segmentation allows the epitaxial process to occur on distributed surfaces, effectively increasing the total contact area available for source/drain formation without requiring a larger overall device footprint.
2Ease of manufacture
If conventional symmetric gate structures are used, then manufacturing is simpler, but the contact area for source/drain growth remains limited
Solution Approach 1:
The patent employs an asymmetric gate structure configuration where the semiconductor cladding layer extends beyond the channel layers on one or more sides, creating an asymmetric source/drain recess geometry. This asymmetry is intentionally designed to maximize the epitaxial growth contact area on the cladding layer while maintaining manufacturability through standard lithography and etching processes that can accommodate the asymmetric pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the contact area for growing the source/drain structure, thereby enhancing the performance of GAA transistors by addressing the limitations of existing technologies.
Implementation Method 1
epitaxially growing a source/drain structure from the channel layers of a second portion of the fin structure and the semiconductor cladding layer
Data Source
AI summary
A semiconductor device includes an active gate structure extending along a first lateral direction. The semiconductor device includes an inactive gate structure also extending along the first lateral direction. The semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. The active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.