GAA Gate Formation Process Window Using a Cladding Layer

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Solution Overview

Problem

Semiconductor fabrication processes face challenges in achieving critical dimension uniformity, particularly as devices shrink, leading to inconsistencies and performance issues in gate structures.

Innovation Solution

The use of a cladding layer, formed either before or after filling a recess in the active channel structure with dielectric material, provides consistent and larger process windows for forming gate structures by ensuring uniformity in gate widths and preventing undesirable effects like overlap shifts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device size is decreased to improve integration density, then productivity and compactness are improved, but manufacturing precision and critical dimension uniformity deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidcritical dimension uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A cladding layer is formed around the active channel structure before gate formation. This preliminary action creates a protective and guiding structure that defines the gate formation region, ensuring uniform gate critical dimensions even as device sizes decrease to improve integration density.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The cladding layer acts as an intermediary structure between the active channel and the gate. It provides a controlled interface that mediates the gate formation process, maintaining critical dimension uniformity while allowing smaller node sizes for higher productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If gate structure formation process window is widened to improve manufacturing precision, then critical dimension uniformity is improved, but device complexity increases

Engineering Contradiction:
Improvecritical dimension uniformityVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The cladding layer is formed in advance before gate deposition, creating a pre-defined template that guides subsequent gate formation. This preliminary structure widens the process window for gate critical dimensions without requiring complex in-situ control during gate deposition.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The cladding layer provides localized structural definition and material properties specifically at the gate formation region. This local quality enhancement ensures uniform gate critical dimensions without complicating the overall device structure or requiring complex processes elsewhere in the device.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12199151B2Process window control for gate formation in semiconductor devices
Publication Date: 2025.01.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12199151B2 patent drawing
  • US12199151B2 patent drawing
  • US12199151B2 patent drawing

AI summary

A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.