GAA Gate Structure With Convex Sidewalls for Interface Reliability
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Solution Overview
Problem
The fabrication of gate-all-around (GAA) transistors introduces new challenges to the semiconductor manufacturing process and raises device reliability concerns due to the formation of high electric field regions at the metal gate-to-source/drain interface, which also leads to poor high-K dielectric deposition and voids.
Innovation Solution
The implementation of a convex sidewall profile for the metal gate layer interfacing the inner spacer, initially formed during a SiGe recess process with a high/low Ge concentration bi-layer epitaxial layer, enhances reliability and improves high-K dielectric deposition by avoiding pointed end tip portions and creating a smooth convex profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-all-around (GAA) transistor structure is implemented to improve gate control and reduce short-channel effects, then device performance is improved, but high electric field regions form at the metal gate-to-source/drain interface causing reliability concerns and poor high-K dielectric deposition
Solution Approach 1:
The patent applies curvature by forming a convex profile on the metal gate layer at the interface with source/drain regions. This convex curvature eliminates the pointed end tip portions that concentrate electric fields, thereby reducing high electric field regions and improving interface reliability while enabling better high-K dielectric deposition.
2Ease of manufacture
If conventional fabrication processes are used for GAA transistors, then manufacturing is simpler, but pointed end tip portions form at the metal gate interface leading to poor high-K dielectric deposition and voids
Solution Approach 1:
The patent changes the geometric parameter of the metal gate sidewall from a conventional flat or pointed profile to a convex profile. This parameter change is achieved through controlled formation processes that create the desired curvature, eliminating pointed end tips and improving both deposition quality and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of the metal gate-to-source/drain interface and facilitates better high-K dielectric deposition, reducing voids and enhancing the overall performance of multi-gate devices like GAA transistors.
Implementation Method 1
a convex sidewall profile for a metal gate layer interfacing an inner spacer, the convex sidewall profile initially formed during a SiGe recess process with a high/low Ge concentration bi-layer epitaxial layer
Data Source
AI summary
A method of fabricating a device includes providing a fin having a plurality of channel layers and a plurality of multilayer epitaxial layers interposing the plurality of channel layers. The multilayer epitaxial layers include a first epitaxial layer interposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers. The method further includes forming an inner spacer between adjacent channel layers. The inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface. The method further includes replacing the multilayer epitaxial layers with a portion of a gate structure.