GAA Gate-Cut Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The integration of gate-all-around (GAA) devices in semiconductor manufacturing is challenging due to complexity in fabricating the GAA features around nanowires/nanosheets, necessitating improved methods for pattern formation and integration.
Innovation Solution
A method involving photolithography and self-aligned processes for double-patterning or multi-patterning to form nanostructure transistors, including the use of sacrificial layers, spacers, and gate-cut structures to improve gate control and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices (GAA) are introduced to improve gate control and reduce short-channel effects, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into multiple discrete steps including forming sacrificial layers, creating spacers, performing selective etching, and depositing gate materials. Each step builds upon the previous one to gradually construct the complex GAA structure, making the overall complex process more manageable and controllable
Solution Approach 2:
Sacrificial layers are formed in advance before the actual gate structure is created. These preliminary structures serve as templates that guide subsequent fabrication steps, enabling precise positioning of the gate-all-around features without requiring direct complex patterning at the final stage
2Productivity
If continuous miniaturization is pursued to improve production efficiency and lower costs, then productivity increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional GAA structures with gates wrapping around channels from multiple directions. This dimensional evolution enables continued scaling by exploiting vertical space and multi-directional gate control, thereby maintaining productivity improvements while managing the inherent complexity through new architectural approaches
3Reliability
If gate-all-around structures are fabricated to maintain gate control during scaling, then device performance is maintained, but integration difficulty increases
Solution Approach 1:
Spacer structures serve as intermediary elements that mediate between the sacrificial layers and the final gate structure. These spacers provide a bridging mechanism that simplifies the integration process by enabling self-aligned formation of the gate-all-around features, reducing the need for complex direct patterning operations
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes forming an isolation structure between a first active region and a second active region, forming a dummy gate structure across channel regions of the first active region and the second active region, patterning the dummy gate structure to form a cut opening corresponding to the isolation structure, forming a wall structure in the cut opening, removing the dummy gate structure to form a gate trench, forming a gate stack in the gate trench, and forming a first gate-cut structure through the wall structure.