GAA Nanostructure Gate Dielectric Layout for Short-Channel Control
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Solution Overview
Problem
As semiconductor technologies progress towards smaller technology nodes, existing gate-all-around (GAA) transistors face challenges in maintaining gate length and reducing short-channel effects (SCE) and parasitic capacitance due to scaled-down critical poly pitch, which complicates epitaxy processes in source/drain regions.
Innovation Solution
The implementation of slimmed high-k gate dielectric layers to increase gate length and distribute space to source/drain regions, allowing for improved epitaxy processes while suppressing SCE and parasitic capacitance by adjusting the thickness of gate dielectric layers on spacers and channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical poly pitch is scaled down to reduce geometry size, then production efficiency is improved and costs are lowered, but gate length is reduced and short-channel effects increase
Solution Approach 1:
The patent applies local quality by creating non-uniform gate dielectric layer thickness: thinner dielectric on spacer regions and thicker dielectric on channel regions. This local differentiation allows the gate length to be extended in channel regions while maintaining scaled-down dimensions in spacer regions, thus resolving the contradiction between reduced geometry size and maintained gate length.
Solution Approach 2:
The patent changes the thickness parameter of the gate dielectric layer spatially, creating a gradient structure where the dielectric thickness varies across different regions. This parameter change enables the gate length to be effectively increased without proportionally increasing the overall device footprint, addressing the contradiction between scaled-down pitch and gate length maintenance.
2Length of stationary object
If the critical poly pitch is scaled down, then geometry size is reduced, but short-channel effects and parasitic capacitance increase
Solution Approach 1:
By implementing locally differentiated gate dielectric thickness, the patent creates enhanced gate control in channel regions through thicker dielectric, which suppresses short-channel effects. Meanwhile, the overall geometry remains scaled down due to thinner dielectric in spacer regions, thus resolving the contradiction between reduced geometry size and suppression of harmful short-channel effects.
3Ease of manufacture
If the gate dielectric layer thickness is uniform, then manufacturing is simplified, but gate length cannot be increased without increasing overall device size
Solution Approach 1:
The patent implements parameter changes by creating a spatially varying gate dielectric thickness profile. This can be achieved through controlled deposition processes that deposit material at different rates or for different durations on different regions, or through selective etching processes. This approach enables gate length extension without proportionally increasing overall device size, while maintaining reasonable manufacturing complexity through established semiconductor fabrication techniques.
Data Source
AI summary
A semiconductor structure includes a substrate, a vertical stack including nanostructures, and a gate structure wrapping around each of the nanostructures. The nanostructures are suspended and vertically arranged over the substrate. The gate structure includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The semiconductor structure further includes inner spacers and gate spacers. The inner spacers are formed on opposite sides of the gate structure, between the nanostructures, and separating the nanostructures from each other. The gate spacers are formed on the opposite sides of the gate structure and over a topmost one of the nanostructures. The gate dielectric layer includes a first portion formed on the nanostructures and a second portion extending from the first portion. The first portion and the second portion have a first thickness and a second thickness, respectively. The first thickness is greater than the second thickness.