Non-Conformal GAA Gate Dielectric Layers for Multi-Vt Reliability
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Solution Overview
Problem
Conventional gate-all-around (GAA) devices face challenges in providing multiple threshold voltages without compromising other performance characteristics, particularly due to damage to gate dielectric layers during processing, which affects reliability and functionality.
Innovation Solution
The method involves forming a gate dielectric layer with an asymmetric thickness profile, where the top sections of the gate dielectric layers have greater thicknesses to mitigate damage during etching operations, while maintaining sufficient thickness on bottom sections for device performance, and using a multi-layer process to achieve this profile through controlled precursor introduction and purging in the processing chamber.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate-all-around devices use uniform thickness gate dielectric layers, then the manufacturing process is simple, but the gate dielectric layers suffer damage during etching operations reducing reliability
Solution Approach 1:
The patent applies asymmetry by forming gate dielectric layers with non-uniform thickness profiles. Specifically, the gate dielectric layer includes a first portion with a first thickness and a second portion with a second thickness that is greater than the first thickness. This asymmetric structure protects the gate dielectric from damage during etching operations while maintaining manufacturing feasibility through selective deposition processes.
Solution Approach 2:
The patent implements local quality by providing different thicknesses of gate dielectric material in different regions. The gate dielectric layer has varying thickness depending on the location: thinner in regions where etching protection is less critical and thicker in regions where damage protection is needed. This localized variation optimizes both reliability and process simplicity.
2Speed
If gate dielectric layers are made thinner to improve device performance, then switching speed increases, but damage during processing increases affecting functionality
Solution Approach 1:
The asymmetric gate dielectric structure allows thin regions to enable fast switching while thick regions provide protection during processing. The first portion has sufficient thickness for speed performance while the second portion has increased thickness to prevent damage during etching operations, resolving the contradiction between speed and processing damage resistance.
Solution Approach 2:
The patent applies beforehand cushioning by pre-forming thicker gate dielectric regions in areas that will be subjected to etching operations. This protective thickness is established before the etching process, cushioning the gate dielectric layer against damage while maintaining thin regions elsewhere for optimal switching performance.
3Adaptability or versatility
If multiple threshold voltages are implemented in GAA devices, then device functionality increases, but gate dielectric damage during processing worsens
Solution Approach 1:
The asymmetric gate dielectric structure supports multiple threshold voltage implementations by providing enhanced protection in regions where additional processing steps are required for multi-Vt fabrication. The varied thickness profile prevents damage during the complex processing sequences needed to achieve multiple threshold voltages, enabling functionality without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes damage to the gate dielectric layers, enhancing the reliability and functionality of GAA devices by maintaining performance characteristics while enabling the fabrication of transistors with different threshold voltages.
Implementation Method 1
the top sections of the gate dielectric layers have greater thicknesses to mitigate damage during etching operations, while maintaining sufficient thickness on bottom sections for device performance
Data Source
AI summary
A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.