Selective High-k Gate Dielectric Thickness in GAA Gate Structures
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing advanced integrated circuits due to the increasing complexity of processing and manufacturing as transistors are scaled down, requiring innovative solutions for efficient production.
Innovation Solution
The development of FinFET devices and gate-all-around (GAA) FET devices, which involve the use of high-k dielectric layers and self-assembling monolayers to improve gate structure and carrier mobility, addresses the challenges of scaling down transistor size while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor geometry size is decreased to increase functional density, then chip area efficiency is improved, but processing and manufacturing complexity increases
Solution Approach 1:
The gate dielectric layer is segmented into different regions with different thicknesses - a first thickness over the fin structure and a second thickness over the mandrel structure. This segmentation allows the gate dielectric to be optimized for different functional requirements, enabling continued scaling while maintaining manufacturability through selective thickness control in different areas.
Solution Approach 2:
Different regions of the gate dielectric layer are given different local properties (thickness values) to optimize performance. The gate dielectric has a thinner region over the fin structure for better electrical control and a thicker region over the mandrel structure for mechanical support and stress management, resolving the complexity issue while enabling further scaling.
2Productivity
If transistor geometry size is decreased to increase functional density, then production efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
A mandrel structure is formed beforehand and used as a template to guide the selective deposition of the gate dielectric layer. This preliminary action creates a built-in pattern that simplifies subsequent manufacturing steps, allowing the gate dielectric to be deposited with different thicknesses in different regions without requiring complex lithography or multiple deposition steps, thus maintaining production efficiency while reducing manufacturing complexity.
Solution Approach 2:
The mandrel structure serves as an intermediary element that facilitates the selective formation of the gate dielectric layer. It acts as a mediator between the deposition process and the final device structure, enabling controlled thickness variation without increasing manufacturing complexity, thereby supporting continued scaling and improved production efficiency.
3Reliability
If gate dielectric thickness is reduced to improve device performance, then carrier mobility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate dielectric layer is formed with different local thicknesses - thinner over the fin structure where high electrical performance is needed and thicker over the mandrel structure where mechanical stability is prioritized. This local quality approach allows optimization of carrier mobility in the active region without imposing stringent thickness control requirements across the entire wafer, reducing manufacturing precision requirements while improving device performance.
Solution Approach 2:
The thickness parameter of the gate dielectric layer is changed locally based on the underlying structure (fin vs. mandrel). By varying this critical parameter spatially rather than uniformly, the invention achieves improved carrier mobility where needed while relaxing overall manufacturing precision requirements, as the deposition process can use standard conditions without requiring ultra-precise thickness control across all regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These technologies enhance chip area efficiency, improve carrier mobility, and facilitate compatible fabrication processes with traditional devices, leading to more efficient and cost-effective production of advanced semiconductor integrated circuits.
Implementation Method 1
A self-assembling monolayer is formed on inner sidewalls of the spacers
Implementation Method 2
A high-k dielectric layer is deposited, wherein a first portion of the high-k dielectric layer on the hydrophilic surface of the interfacial layer is thicker than a second portion of the high-k dielectric layer on the hydrophobic surface of the self-assembling monolayer
Data Source
AI summary
A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.