GAA Nanowire Gate Stacks With Additive Metal Gate Endcap Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit fabrication is achieving uniform threshold voltages and tight gate endcap tolerances, especially for gate-all-around (GAA) architectures, where conventional subtractive metal gate flows face issues with isotropic wet etch bias and aggressive chemistries, leading to inefficient transistor density and non-uniform voltage characteristics.
Innovation Solution
The implementation of an additive metal gate flow (AMGF) process, which involves depositing a high-temperature hard mask, patterning, and then depositing work function metal layers both on open and blocked areas, allows for precise control of gate endcaps and uniform threshold voltages, thereby overcoming the limitations of subtractive metal gate flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional subtractive metal gate flows are used, then manufacturing simplicity is maintained, but gate endcap tolerances become loose and threshold voltage uniformity deteriorates
Solution Approach 1:
The patent inverts the conventional subtractive metal gate approach by using an additive process. Instead of depositing metal and then removing excess material, the process deposits work function metal layers only in the desired gate regions using a high-temperature hard mask that protects unwanted areas. This inversion enables tight gate endcap tolerances (≤10-15 nm) and uniform threshold voltages across all nanowire sides, resolving the precision-complexity contradiction.
2Productivity
If isotropic wet etch bias is used in subtractive processes, then manufacturing is simplified, but transistor density efficiency decreases due to aggressive chemistries
Solution Approach 1:
The patent extracts the problematic isotropic wet etch step from the process by eliminating the subtractive approach entirely. The additive metal gate flow deposits work function metals (TiN, TaN) and conductive fills ( tungsten, cobalt, copper) only where needed, protected by a high-temperature hard mask, removing the need for aggressive etching chemistries that reduce transistor density efficiency.
3Productivity
If feature dimensions are scaled down, then device density increases, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent moves the patterning challenge from the lateral lithographic dimension to the vertical deposition dimension. By using a high-temperature hard mask and conformal deposition of work function metals in the vertical direction, the process achieves precise gate endcap definition (≤10-15 nm) without being constrained by lithographic resolution limits, enabling continued scaling while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The AMGF process enables the achievement of tight gate endcap tolerances (≤10-15 nm) and uniform threshold voltages across all nanowire sides, resulting in high transistor density and efficient transistor performance for advanced semiconductor processing nodes.
Implementation Method 1
depositing work function metal layers both on open and blocked areas
Implementation Method 2
depositing a high-temperature hard mask, patterning
Data Source
AI summary
An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and “Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.