Metal Gate Fill Layers for Low-Resistance GAA Gate Control
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Solution Overview
Problem
Conventional gate-all-around (GAA) transistors face challenges with excessive resistance and work function variations, which degrade device performance and complicate fabrication due to limited channel-to-channel spacings and material optimization issues for nanometer-scale features.
Innovation Solution
The introduction of new gate fill metal materials with low resistance, suitable stress effects, and work functions, such as ruthenium (Ru), iridium (Ir), osmium (Os), rhodium (Rh), and nickel (Ni), which provide improved performance by reducing resistance, simplifying device structures, and enabling halogen-free processes, thereby enhancing reliability and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GAA devices are fabricated, then gate control is improved, but resistance becomes excessive and work function variations increase
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional materials to tungsten, which has superior properties for reducing resistance and minimizing work function variations. This material substitution directly addresses the contradiction by improving electrical performance while maintaining fabrication compatibility
Solution Approach 2:
The patent employs composite gate electrode structures combining tungsten with other materials to achieve optimal performance. The composite approach allows simultaneous optimization of resistance, work function stability, and stress control, resolving the contradictions through synergistic material properties
2Reliability
If conventional GAA devices are fabricated, then gate control is improved, but fabrication complexity increases due to material optimization issues
Solution Approach 1:
The patent changes the material parameter to tungsten, which has favorable fabrication characteristics including compatibility with existing CMOS processes. This simplifies the fabrication process by eliminating material optimization issues while maintaining superior gate control
Solution Approach 2:
The patent adopts tungsten as a readily available material that can be deposited using standard industrial processes. This approach reduces fabrication complexity by utilizing well-established, cost-effective deposition techniques rather than requiring complex material optimization procedures
3Reliability
If new gate fill metal materials are introduced, then resistance is reduced, but additional layers may be required
Solution Approach 1:
The tungsten gate electrode performs multiple functions in a single layer: it provides low resistance, enables stress control, and serves as the gate electrode itself. This multi-functionality reduces the need for additional layers while achieving superior electrical performance
Solution Approach 2:
The patent merges the functions of resistance reduction and stress control into a single tungsten gate electrode material. This consolidation eliminates the need for separate functional layers, thereby reducing device structural complexity while maintaining low resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These materials achieve lower resistivities and suitable stress effects, improving carrier mobility and simplifying device fabrication, leading to enhanced performance and reliability of GAA devices while eliminating the need for additional layers, thus reducing production complexity and costs.
Implementation Method 1
These materials achieve lower resistivities and suitable stress effects, improving carrier mobility
Implementation Method 2
suitable stress effects, which degrade device performance
Data Source
AI summary
An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.