GAA Nanosheet Gate Structure With Hard Mask Isolation Protection
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Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) devices face challenges such as loss of materials from isolation structures during the nanosheet release process, leading to undesired parasitic capacitances that degrade the performance of GAA transistors in memory and standard logic cells.
Innovation Solution
Incorporating hard mask layers over isolation structures to prevent material loss and ensure proper formation of the gate structure, which wraps around the base fins without extending deeply between them, thereby minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to manufacture GAA devices, then fabrication process is simpler, but material loss from isolation structures occurs leading to increased parasitic capacitance
Solution Approach 1:
A hard mask layer is formed over the isolation structure before the nanosheet release process. This preliminary protective action prevents material loss from the isolation structure during subsequent etching, thereby reducing parasitic capacitance without complicating the overall fabrication flow
Solution Approach 2:
The hard mask layer acts as an intermediary protective layer between the isolation structure and the etching process. It mediates the interaction by providing a barrier that prevents direct etching of the isolation structure, thus preventing material loss and reducing parasitic capacitance
2Reliability
If gate structure extends deeply between base fins, then better coverage is achieved, but parasitic capacitance increases degrading transistor performance
Solution Approach 1:
The hard mask layer provides localized protection to the isolation structure in critical regions between base fins. This allows the gate structure to be properly formed with adequate coverage while preventing material loss in specific areas that would otherwise increase parasitic capacitance
3Productivity
If isolation structure material is lost during nanosheet release, then process is simpler, but transistor performance degrades due to increased parasitic capacitance
Solution Approach 1:
The hard mask layer is applied in advance before the nanosheet release process to protect the isolation structure. This preliminary action ensures that material loss is prevented during the release process, maintaining transistor performance without reducing process efficiency
Data Source
AI summary
A method for manufacturing a semiconductor structure includes forming fins over a substrate. Each of the fins includes a base fin protruding from the substrate, and first semiconductor layers and second semiconductor layers alternating stacked over the base fin. The method further includes forming an isolation structure between the base fins, forming a hard mask layer over the isolation structure, and removing the second semiconductor layers, so that the first semiconductor layers and the hard mask layer are exposed in a gate trench. The method further includes forming a gate structure in the gate trench. The gate structure wraps around the first semiconductor layers and over the hard mask layer.