Gate-All-Around Gate Stack With Reduced Height and Lower Capacitance

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Solution Overview

Problem

The challenge in integrated circuit manufacturing lies in scaling multi-gate and nanowire transistors below the 10 nanometer node, where the trade-off between feature dimension and spacing constraints limits performance optimization, particularly due to the additional gate height caused by the presence of a dielectric capping material in gate-all-around structures.

Innovation Solution

The dielectric capping material is removed from the top of the fin inside the gate stack post-dummy gate patterning, reducing the gate height and minimizing capacitance, thereby enhancing operating speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If dielectric capping material is present in gate-all-around structures, then structural integrity and fabrication ease are improved, but gate height increases causing increased capacitance and reduced operating speed

Engineering Contradiction:

Improvefabrication easeVSAvoidoperating speed

Core Design Contradiction:

Ease of manufactureVSSpeed

Solution Approach 1:

The dielectric capping material is selectively removed from the top surface of the fin inside the gate stack through selective etching processes. This extraction eliminates the harmful capacitance effect while preserving the material's protective function in other regions, thereby resolving the contradiction between fabrication ease and operating speed.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The dielectric capping material is retained in certain locations (outside the gate stack) while being removed in specific locations (inside the gate stack). This local differentiation allows the structure to maintain structural integrity where needed while eliminating capacitance where it harms performance, thus resolving the contradiction.

Inventive Principle:

Principle #3Local quality

2Speed

If dielectric capping material is removed from top of fin inside gate stack, then gate height is reduced and capacitance is minimized, but additional process steps are required

Engineering Contradiction:

Improveoperating speedVSAvoidprocess complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The dielectric capping material is removed at an optimized point in the fabrication sequence—after dummy gate patterning but before final gate formation. This preliminary action allows subsequent processes to benefit from the reduced gate height without requiring complete process rework, thus minimizing the impact of additional steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Selective etching processes with appropriate masking serve as intermediary steps that enable precise removal of the dielectric material only where needed. These intermediary processes bridge the gap between the conflicting requirements by providing controlled, localized modification without disrupting the overall fabrication flow.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12563779B2Gate-all-around integrated structures having gate height reduction and dielectric capping material with shoulder portions inside gate stack

Publication Date: 2026.02.24 INTEL CORP

AI summary

Gate-all-around integrated circuit structures having reduced gate height structures and subfins, and method of fabricating gate-all-around integrated circuit structures having reduced gate height structures, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a subfin, and an isolation structure on either side of the subfin. A gate stack is over the plurality of nanowires, around individual nanowires, and over the subfin. Gate spacers are on either side of the gate stack, and a dielectric capping material is inside the gate spacers with shoulder portions inside the gate stack.