GAA Metal Gate Height Control for Short-Channel Suppression
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Solution Overview
Problem
Integration of gate-all-around (GAA) transistor structures in semiconductor devices is challenging due to difficulties in fabrication, particularly in achieving precise patterning and control of gate height, which affects gate-channel coupling and short-channel effects.
Innovation Solution
A method involving photolithography and self-aligned processes for patterning GAA structures, including the use of sacrificial layers and spacers, followed by selective etching and deposition of metal gate layers with controlled height, to improve yield and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for GAA structures, then manufacturing process is simpler, but gate control precision and yield are insufficient
Solution Approach 1:
The gate structure is divided into multiple segments including a first gate structure and a second gate structure formed at different stages. The first gate structure is formed initially, then a second gate structure is formed afterward to achieve precise height control. This segmentation allows independent optimization of each gate portion without requiring complete redesign of the entire fabrication process.
Solution Approach 2:
A preliminary gate structure is formed before the final gate structure. The first gate structure serves as a preliminary element that establishes the basic configuration, and subsequent processing steps build upon this foundation to achieve the final precise gate height. This preliminary action enables better control over the final gate dimensions.
2Reliability
If gate height is increased to improve gate control, then gate-channel coupling improves, but short-channel effects worsen
Solution Approach 1:
Different regions of the gate structure are given different properties through the first and second gate structures. The first gate structure provides one set of electrical characteristics while the second gate structure provides another, allowing local optimization of gate control in specific regions without uniformly increasing overall gate height that would exacerbate short-channel effects.
Solution Approach 2:
The gate structure employs asymmetric configuration with the first gate structure and second gate structure having different characteristics. This asymmetry allows tailored control of gate-channel coupling in different areas, achieving improved reliability in specific regions while maintaining acceptable short-channel effect performance overall.
Data Source
AI summary
A semiconductor device structure includes first nanostructures and second nanostructures over a substrate. The semiconductor device structure also includes a first metal gate layer surrounding the first nanostructures. The semiconductor device structure further includes a second metal gate layer surrounding the second nanostructures and over the first metal gate layer. The first metal gate layer comprises N-work-function metal, and the second metal gate layer comprises P-work-function metal.