GAA Nanosheet Gate Structure With Variable Isolation Thickness
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Solution Overview
Problem
Existing technologies for fabricating gate-all-around (GAA) transistors in integrated circuits face challenges in managing active area space and gate structure shape, which impact source/drain feature bridge margin and performance as they are scaled down.
Innovation Solution
The implementation of reduced active area space and varied isolation structure thicknesses in GAA transistor fabrication, utilizing methods like double-patterning or multi-patterning processes, to improve process margin and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If reduced active area space is used in GAA transistor fabrication, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (double-patterning or multi-patterning) to achieve the required precision. This segments the complex task of creating precise source/drain features into manageable sequential steps, where each step creates a portion of the final pattern, thereby improving manufacturing precision without requiring the entire complex structure to be formed in a single step.
Solution Approach 2:
The patent utilizes vertical stacking of nanosheets in the GAA transistor structure, transitioning from a planar 2D approach to a 3D vertical architecture. This dimensional change allows for reduced active area footprint while maintaining electrical performance, as the channel length is extended in the vertical dimension rather than requiring larger lateral dimensions.
2Manufacturing precision
If varied isolation structure thicknesses are implemented, then manufacturing precision is improved, but ease of manufacture decreases
Solution Approach 1:
Different isolation structures are assigned different thicknesses based on their specific location and functional requirements within the device. This local quality approach allows each isolation region to be optimized for its particular purpose (e.g., stress management, electrical isolation, mechanical support) rather than using a uniform thickness, thereby improving overall process margin and device performance.
Solution Approach 2:
The isolation structures are formed with predetermined varying thicknesses as part of the initial fabrication sequence, before subsequent processing steps. This preliminary action establishes the correct geometric foundations early in the manufacturing process, preventing the need for complex post-processing adjustments and actually simplifying later steps despite the initial complexity of forming varied thicknesses.
Data Source
AI summary
A semiconductor device includes a first circuit cell, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first circuit cell includes a first active area in a first well in a substrate, a second active area in a second well in the substrate, and a first gate structure wrapping around nanostructures in the first active area and the second active area. The first dielectric layer is over the first well. The second dielectric layer is over the first well and the second well. The third dielectric layer is over the second well. The first dielectric layer, the second dielectric layer, and the third dielectric layer are under and in contact with the first gate structure. A thickness of the second dielectric layer is less than thicknesses of the first dielectric layer and the third dielectric layer.