GAA Channel Layer Layout to Limit Gate Length Enlargement
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Solution Overview
Problem
Current semiconductor devices with gate-all-around (GAA) structures face challenges in reducing gate length enlargement, which affects their alternating current (AC) characteristics and manufacturing efficiency.
Innovation Solution
The semiconductor device design includes a substrate with channel layers and embedded source/drain layers, where the gate electrode surrounds the channel layers, and the channel layers have varying lengths to optimize AC characteristics, with a manufacturing method involving fin structure formation, dry etching, and epitaxial layer growth to reduce gate length and enhance AC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a gate-all-around (GAA) structure is used to increase semiconductor device density, then device density and current control ability are improved, but gate length enlargement occurs which deteriorates AC characteristics
Solution Approach 1:
The gate electrode is segmented into multiple sections along the channel length, with each section having independently controllable length. This allows the gate to wrap around the nanowire channel in multiple regions while maintaining controlled gate length in each segment, thereby achieving high device density through GAA structure while preventing excessive gate length enlargement that would harm AC characteristics
Solution Approach 2:
Different sections of the gate electrode are designed with different local properties - some sections have longer gate length for enhanced control, while others have shorter gate length to maintain AC performance. The gate length varies locally along the channel, optimizing both density and electrical characteristics in different regions
2Reliability
If the gate electrode completely surrounds the nanowire channel to achieve gate-all-around structure, then current control ability is improved, but manufacturing complexity increases
Solution Approach 1:
The nanowire channel is formed first as a complete surrounding structure, and then the gate electrode is deposited to wrap around it. This preliminary formation of the nanowire ensures that the gate-all-around structure is achieved systematically, improving current control ability while managing manufacturing complexity through a structured sequential process
Solution Approach 2:
The gate electrode is formed as a nested structure that completely surrounds the nanowire channel, with the gate wrapping around the channel in multiple layers or sections. This nested configuration achieves comprehensive gate control while organizing the manufacturing process into manageable sequential steps, reducing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces gate length enlargement, improving AC characteristics and facilitating a more efficient manufacturing process for semiconductor devices.
Implementation Method 1
forming recesses on opposing sides of the dummy gate by anisotropically dry etching the fin structure
Implementation Method 2
extending the recesses using an isotropic dry etching process to form extended recesses
Data Source
AI summary
A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.