GAA Transistor Gate Layout With Multiple Lengths for Lower Rext
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Solution Overview
Problem
GAA transistors face challenges with high extension resistance (Rext) in the source/drain extension region, which degrades device performance, particularly in the bottommost channel member, due to uniform gate lengths and spacer configurations.
Innovation Solution
The formation of GAA transistors with varying gate lengths and spacer widths by using sacrificial layers with different germanium concentrations, allowing selective etching to create distinct gate lengths and spacer features, reducing Rext and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform gate lengths and spacer configurations are used in GAA transistors, then fabrication process simplicity is maintained, but extension resistance in the source/drain extension region becomes high, degrading device performance
Solution Approach 1:
The patent applies local quality by implementing non-uniform gate lengths where different portions of the gate structure have different lengths. Specifically, the gate length is reduced in regions corresponding to the source/drain extension regions while maintaining longer gate lengths in other regions. This localized modification reduces parasitic resistance in critical areas without requiring complete redesign of the entire gate structure, thus improving device performance while limiting complexity increase.
Solution Approach 2:
The gate structure is segmented into multiple regions with different gate lengths. The patent divides the gate into at least two distinct segments: a first region with a first gate length and a second region with a second gate length. This segmentation allows independent optimization of different gate regions to address the extension resistance problem in specific areas while maintaining appropriate control in other areas.
2Reliability
If non-uniform gate lengths are implemented to reduce extension resistance, then device performance improves, but fabrication process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming a sacrificial layer with a specific profile before forming the gate structure. The sacrificial layer is deposited and patterned to create the desired non-uniform gate length configuration in advance. Subsequent removal of the sacrificial layer reveals the pre-configured gate structure, allowing complex gate length variations to be achieved through relatively simple subsequent processing steps.
Solution Approach 2:
The patent uses a sacrificial layer as an intermediary to achieve the non-uniform gate length configuration. The sacrificial layer is deposited conformally and then selectively removed to define the different gate lengths. This intermediary approach allows the complex gate structure to be formed using standard deposition and etching processes, avoiding the need for complex lithography or multiple patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic resistance and improves drive current in GAA transistors by optimizing gate lengths and spacer configurations, while maintaining compatibility with existing fabrication processes.
Implementation Method 1
using sacrificial layers with different germanium concentrations, allowing selective etching to create distinct gate lengths and spacer features
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped active region over a substrate and comprising a number of channel layers interleaved by a number of sacrificial layers, removing a source/drain region of the fin-shaped active region to form a source/drain opening, forming a source/drain feature in the source/drain opening, selectively removing the number of sacrificial layers to form a number of gate openings, and forming a gate structure in the number of gate openings, where the gate structure includes a first portion formed in a first gate opening of the number of gate openings and a second portion formed in a second gate opening of the number of gate openings, a gate length of the first portion is different from a gate length of the second portion.