GAA Gate Metal Neck Retraction for Low-Capacitance Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor manufacturing process faces increased complexity due to the scaling down of integrated circuits, necessitating advancements in manufacturing processes to maintain efficiency and reduce costs.
Innovation Solution
A gate-all-around (GAA) transistor structure is manufactured using a multi-patterning process, involving a sacrificial layer and self-aligned spacers to form nanostructures, with a gate structure wrapping around the channel regions for improved control of current flow, and a specific etching and deposition sequence to form a gate metal layer and gate spacer configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into multiple patterning steps (first pattern formation, second pattern formation) with intermediate etching and deposition steps. This segmentation allows complex GAA transistor structures to be built through manageable sequential operations, reducing the effective complexity of each individual step while achieving high functional density through cumulative patterning.
Solution Approach 2:
Sacrificial layers are formed and positioned in advance before the final gate structure is created. These preliminary structures guide subsequent self-aligned spacer formation and material deposition, ensuring precise positioning of the gate-all-around structure without requiring complex real-time alignment procedures.
2Reliability
If gate structure wraps around channel regions for improved current control, then electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure is formed by nesting multiple layers and materials around the channel region in a sequential manner. The self-aligned spacers are deposited conformally around sacrificial structures, then subsequent gate materials are deposited around the spacers, creating a nested configuration that achieves complete gate wrap-around through layered assembly rather than complex monolithic formation.
Solution Approach 2:
Self-aligned spacers serve as intermediary structures that mediate between the sacrificial layers and the final gate material. These spacers provide the necessary spacing and alignment references for forming the gate-all-around structure, enabling precise control of gate positioning without direct complex patterning of the gate material itself.
3Manufacturing precision
If multi-patterning process is used to form GAA transistor structure, then device performance is improved, but manufacturing steps increase
Solution Approach 1:
Self-aligned spacers are formed through conformal deposition processes that automatically position themselves relative to the sacrificial structures without requiring additional alignment steps. The deposition process itself provides the alignment function, making the system self-aligning and reducing the need for complex external alignment procedures between patterning steps.
Data Source
AI summary
A semiconductor device includes a substrate, a shallow trench isolation structure, two epitaxial structures, one or more semiconductor channel layers, a gate metal layer and a gate spacer. The shallow trench isolation structure is disposed over the substrate. The epitaxial structures are disposed over the shallow trench isolation structure. The one or more semiconductor channel layers connect the two epitaxial structures. The gate metal layer is located between the epitaxial structures and engages the one or more semiconductor channel layers. The gate spacer is in contact with a sidewall of the gate metal layer. From a cross-section view, a neck portion of the gate metal layer adjacent to and along the one or more semiconductor channel layers, and one side of the neck portion is retracted by a distance relative to the gate spacer, and the distance is greater than 0 and less than or equal to 2 nanometers.