GAA Nanosheet Gate Oxide Thickness Split for Core and I/O Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in continuously scaling down gate stacks for input/output (I/O) and core devices with varying gate oxide layer thicknesses to suit different applications, as existing multiple gate field-effect transistors and processes are not entirely satisfactory for high-voltage and high-speed applications.
Innovation Solution
The implementation of gate-all-around (GAA) devices with vertically stacked nanosheet channels, where the GAA device in the core area has a thin gate oxide layer for high-speed applications and a thicker gate oxide layer in the I/O area for high-voltage applications, along with a flexible design integration scheme that accommodates different circuits on the same IC substrate, using a method that includes forming gate spacers, semiconductor structures, and an annealing process to increase the gate oxide layer thickness in the I/O area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a thin gate oxide layer is used for core devices, then high-speed performance is improved, but high-voltage capability deteriorates
Solution Approach 1:
The patent applies local quality by forming different gate oxide layer thicknesses in different regions of the same semiconductor device. Specifically, a first gate oxide layer with thickness T1 is formed in the core device region, while a second gate oxide layer with thickness T2 (where T2 > T1) is formed in the I/O device region. This allows core devices to operate at high speeds with thin oxide layers while I/O devices provide high-voltage capability with thicker oxide layers, resolving the contradiction between speed and voltage capability.
2Reliability
If a thick gate oxide layer is used for I/O devices, then high-voltage capability is improved, but high-speed performance deteriorates
Solution Approach 1:
The patent implements local quality by spatially differentiating the gate oxide layer thickness across different functional regions. The I/O device region receives a thicker gate oxide layer (T2) optimized for high-voltage operation, while the core device region receives a thinner gate oxide layer (T1) optimized for high-speed operation. This regional differentiation allows each device type to operate at its optimal performance point without compromising the other.
3Reliability
If different gate oxide layer thicknesses are used for different device regions, then device performance is improved, but process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor substrate into distinct regions (core device region and I/O device region) and forming gate oxide layers with different thicknesses in each region. This is achieved through selective deposition or etching processes that target specific regions, allowing independent optimization of gate oxide thickness for each device type while maintaining a unified fabrication workflow.
Solution Approach 2:
The patent implements local quality by applying different gate oxide layer thicknesses to different functional regions of the semiconductor device. The core device region is equipped with a thin gate oxide layer (T1) for high-speed operation, while the I/O device region is equipped with a thick gate oxide layer (T2) for high-voltage operation. This regional customization optimizes device performance without requiring entirely separate fabrication processes.
4Adaptability or versatility
If multiple gate oxide layer thicknesses are integrated on the same substrate, then circuit design flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the substrate into distinct functional regions and forming gate oxide layers with different thicknesses in each region. This regional approach allows the use of standard deposition or etching processes with modified parameters for each region, achieving precise thickness control (T1 for core devices, T2 for I/O devices) while maintaining overall process compatibility and reducing the need for entirely separate fabrication lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of high-speed and high-voltage transistors on the same substrate, enabling optimized circuit design by varying gate oxide thicknesses, improving performance and manufacturing efficiency while maintaining compatibility with existing semiconductor manufacturing flows.
Implementation Method 1
performing an annealing process to increase a thickness of the second oxide layer under the capping layer
Data Source
AI summary
A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.