GAA Gate Work Function Patterning for Uniform Threshold Voltage
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Solution Overview
Problem
Challenges exist in patterning gate work function metal layers for gate-all-around (GAA) devices due to the narrow space between adjacent channel semiconductor layers, leading to variations in threshold voltage (Vt) and increased complexity in CMOS process flows.
Innovation Solution
A method for fabricating multi-gate devices that involves forming a sacrificial layer, etching it selectively in specific regions, and then depositing n-type and p-type work function metal layers with optional passivation layers to ensure uniform Vt distribution and compatibility with existing CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate patterning is used in GAA devices, then manufacturing process simplicity is maintained, but threshold voltage uniformity deteriorates due to narrow space between adjacent channel layers
Solution Approach 1:
The gate patterning process is segmented into multiple discrete steps: forming sacrificial layers in specific regions, selectively etching sacrificial layers from n-type or p-type regions, depositing work function metal layers in exposed regions, and forming passivation layers. This segmentation allows precise control of metal distribution in narrow spaces between channel layers, improving threshold voltage uniformity while managing process complexity through systematic breakdown of the patterning challenge
Solution Approach 2:
Sacrificial layers are formed in advance in specific regions (n-type or p-type) before work function metal deposition. This preliminary action prepares the structure by occupying spaces where metal should not be deposited, ensuring that when work function metal is later deposited, it only forms in the intended regions. This advance preparation is critical for achieving uniform threshold voltage in the narrow spaces between adjacent channel layers
2Ease of manufacture
If work function metal layers are deposited without selective region control, then processing steps are reduced, but metal distribution uniformity deteriorates leading to Vt variations
Solution Approach 1:
Sacrificial layers act as intermediary elements that temporarily occupy specific regions during the fabrication process. These intermediaries prevent work function metal from depositing in regions where it should not be present, ensuring uniform metal distribution. After metal deposition, the sacrificial intermediaries are removed, leaving the desired metal pattern. This intermediary approach maintains process simplicity while achieving precise metal distribution control
Solution Approach 2:
The fabrication process applies different treatments to different regions: n-type regions receive n-type work function metal while p-type regions receive p-type work function metal. Passivation layers are selectively formed in specific regions to protect metal layers. This local differentiation ensures that each region receives the appropriate metal type and protection, achieving uniform metal distribution and threshold voltage across the device while maintaining relatively simple processing through region-specific customization
3Productivity
If GAA devices are scaled down to maintain gate control, then device performance improves, but fabrication challenges increase due to tighter spacing between channels
Solution Approach 1:
The gate structure transitions from planar 2D gating to 3D gate-all-around configuration, where the gate wraps around the channel in multiple dimensions. This dimensional change provides superior gate control over the channel, enabling continued scaling. The segmented patterning process with sacrificial layers extends this control to the vertical and lateral dimensions, allowing precise metal deposition in the confined 3D space between scaled-down channels while managing fabrication complexity
Data Source
AI summary
A device includes a substrate, channel layers over the substrate, a gate dielectric layer around the channel layers, a first work function metal layer around the gate dielectric layer, a second work function metal layer over the first work function metal layer, and a passivation layer between the first work function metal layer and the second work function metal layer. The passivation layer merges in space vertically between adjacent ones of the channel layers.