GAA Transistor Gate Structure With Recessed Isolation Capacitance Control
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Solution Overview
Problem
Current methods for integrating gate-all-around (GAA) transistor features around nanowires face challenges in fabrication, requiring improvements to enhance gate control and reduce parasitic capacitance and short-channel effects.
Innovation Solution
The method involves forming a semiconductor device structure by alternating semiconductor material layers over a substrate, patterning fin structures, forming isolation and dummy gate structures, and etching to create recesses for source/drain epitaxial growth, followed by removing the dummy gate and etching back isolation material to reduce parasitic capacitance and enhance gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the dummy gate structure is removed after epitaxial growth, then source/drain regions can be formed, but the dummy gate may collapse during subsequent etching processes
Solution Approach 1:
The method performs preliminary actions by forming the dummy gate structure early in the fabrication process, allowing it to serve as a template for subsequent epitaxial growth of source/drain regions. The dummy gate is designed with preliminary structural features (such as being formed over a sacrificial layer that maintains spacing) that prevent collapse during later etching operations.
2Object-affected harmful factors
If isolation material is completely removed to reduce parasitic capacitance, then gate control is improved, but the structural support is lost
Solution Approach 1:
The method selectively extracts or removes the isolation material from specific regions where it contributes to parasitic capacitance, while deliberately leaving it intact in other regions where it provides necessary structural support. This selective removal allows the gate structure to be formed with improved electrical characteristics while maintaining structural integrity through retained isolation material in critical areas.
Data Source
AI summary
A method for forming a semiconductor device structure includes forming fin structures over a substrate. The method also includes depositing an isolation material surrounding the fin structures. The method also includes forming a dummy gate structure across the fin structure. The method also includes growing source/drain epitaxial structures over opposite sides of the dummy gate structure. The method also includes removing the dummy gate structure. The method also includes recessing the isolation material after removing the dummy gate structure. The method also includes forming a gate structure over the isolation material.