GAA Gate Electrode Formation With Slanted Sidewall Spacers
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes, particularly in forming gate all around (GAA) transistors, is increased by the need for precise patterning and high integration density, which existing methods struggle to efficiently manage, leading to challenges in achieving satisfactory electrical properties and uniform gate electrode formation.
Innovation Solution
A manufacturing method involving alternating epitaxial growth, patterning, and spacer etching processes to form fin stacks with specific semiconductor layers, followed by spacer etching to widen gate trenches, allowing for the formation of gate electrodes that laterally surround channel regions, enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning methods are used for GAA transistor fabrication, then manufacturing process complexity is reduced, but gate electrode uniformity and electrical properties deteriorate
Solution Approach 1:
The manufacturing process is divided into multiple sequential stages: forming alternating semiconductor layers, creating dummy structures, depositing spacers, selective removal of dummy structures, and gate electrode formation. Each stage prepares the structure for the next, breaking down the complex GAA transistor fabrication into manageable steps that achieve precise gate electrode uniformity while maintaining overall process control
Solution Approach 2:
Dummy structures are formed in advance before the actual gate electrode formation. These dummy structures serve as placeholders that define the gate trench positions and dimensions. By preparing these structures preliminarily, the subsequent gate electrode formation can proceed with precise alignment and uniformity without requiring complex real-time adjustments
2Productivity
If high integration density is achieved through scaling down, then device functionality is improved, but manufacturing process complexity increases
Solution Approach 1:
Multiple functions are combined into single process steps where possible. For example, the spacer deposition step simultaneously defines gate trench boundaries, protects channel regions, and establishes gate electrode dimensions. The alternating semiconductor layer formation creates both channel structures and sacrificial layers in one epitaxial process, reducing the total number of fabrication steps while achieving high integration density
Solution Approach 2:
The spacer structures self-align to the dummy structures through conformal deposition, automatically defining precise gate trench positions without requiring additional alignment steps. The alternating semiconductor layers self-organize into channel and sacrificial regions through selective etching, eliminating the need for separate patterning steps for each layer type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the quality and uniformity of gate electrodes, particularly in short channel regions, by expanding the process window for gate electrode formation, reducing voids and defects, and enhancing the electrical properties of transistors.
Implementation Method 1
a first stack having first semiconductor sheets and first replaceable semiconductor sheets in alternation is formed
Data Source
AI summary
A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate, semiconductor channel sheets disposed over the semiconductor substrate, and source and drain regions located beside the semiconductor channel sheets. A gate structure is disposed between the source and drain regions and disposed over the semiconductor channel sheets. The gate structure laterally surrounds the semiconductor channel sheets. The gate structure includes a top gate electrode structure disposed above the semiconductor channel sheets, and lower gate electrode structures disposed between the semiconductor channel sheets. Sidewall spacers are disposed between the gate structure and source and drain regions, and the sidewall spacers located next to the top gate electrode structure have slant sidewalls.