Gate-All-Around FET Gate Structure With Sloped Contact Sidewalls

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Solution Overview

Problem

The semiconductor industry faces challenges in shrinking the size and increasing the speed of field-effect transistors (FETs), particularly in forming gate-all-around FETs with existing patterning methods that limit the creation of smaller, more efficient transistor structures.

Innovation Solution

The method involves forming conical frustum-shaped gate electrodes and source/drain pickup regions with sloped sidewalls using multi-patterning processes, including photolithography and self-aligned techniques, to enhance contact area and flexibility for gate and source/drain contacts, allowing for improved transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If conventional patterning methods are used to form gate-all-around FETs, then existing manufacturing processes can be maintained, but the transistor size cannot be sufficiently reduced and speed increased

Engineering Contradiction:

Improvetransistor sizeVSAvoidpatterning process complexity

Core Design Contradiction:

Length of moving objectVSEase of manufacture

Solution Approach 1:

The gate electrode formation process is segmented into multiple patterning steps, where a first pattern is formed and then a second pattern is formed using self-aligned techniques. This segmentation allows achieving smaller transistor dimensions while maintaining manufacturing feasibility through systematic process breakdown.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from planar patterning to three-dimensional gate-all-around structures. The gate electrode completely surrounds the channel region in multiple dimensions, enabling superior electrical control and smaller effective channel dimensions compared to conventional planar gates.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If gate-all-around structures are formed to increase speed, then transistor performance improves, but contact area and contact resistance become critical challenges

Engineering Contradiction:

Improvetransistor switching speedVSAvoidcontact area precision

Core Design Contradiction:

SpeedVSManufacturing precision

Solution Approach 1:

The gate electrode and source/drain regions are formed with sloped sidewalls rather than vertical profiles. This curvature increases the lateral surface area available for contacts, reducing contact resistance while maintaining the compact three-dimensional gate-all-around structure for high-speed operation.

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The sidewall angle parameter is optimized to create sloped profiles. By changing the geometric parameter from vertical to sloped, the contact area is increased and contact resistance is reduced, directly addressing the performance challenge of gate-all-around FETs.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12094946B2Gate all around device

Publication Date: 2024.09.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device includes a nanostructure, a gate dielectric layer, a gate electrode, and a gate contact. The nanostructure is over a substrate. The gate dielectric layer laterally surrounds the nanostructure. The gate electrode laterally surrounds the gate dielectric layer. The gate electrode has a bottom surface and a top surface both higher than a bottom end of the nanostructure. The gate electrode has a horizontal dimension decreasing from the bottom surface to the top surface. The gate contact is electrically coupled to the gate electrode.