GAA Transistor Gate Spacer Layout for Lateral Etching Control
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Solution Overview
Problem
Existing methods for forming gate-all-around (GAA) FET devices face challenges in accurately controlling the dimensions of the active gate structure due to discrepancies in etching rates between the dummy gate structure and sacrificial layers, leading to lateral etching issues that impact gate controllability.
Innovation Solution
The method involves forming an intermediate structure with etching characteristics similar to sacrificial layers, ensuring that its thickness matches the sacrificial layers, thereby controlling lateral etching amounts and maintaining accurate dimensions before forming the inner spacer and active gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy gate structure is formed over semiconductor layers with sacrificial layers, then the gate structure can be subsequently formed, but discrepancies in etching rates between the dummy gate structure and sacrificial layers cause lateral etching issues that reduce manufacturing precision
Solution Approach 1:
An intermediate structure is introduced between the dummy gate structure and the active gate structure. This intermediate structure has etching characteristics similar to the sacrificial layers, acting as a mediator that enables synchronized etching removal with the sacrificial layers, thereby preventing lateral etching discrepancies and improving manufacturing precision of the active gate structure dimensions.
2Productivity
If the dummy gate structure and sacrificial layers are etched simultaneously, then the process efficiency is improved, but the different etching rates lead to dimensional inaccuracies
Solution Approach 1:
The intermediate structure serves as a mediator that enables simultaneous etching of the dummy gate structure and sacrificial layers at matching rates. By having the intermediate structure's etching characteristics resemble those of the sacrificial layers, both can be removed together in the same etching process step, maintaining high productivity while achieving precise dimensional control of the active gate structure.
3Manufacturing precision
If the thickness of the intermediate structure is controlled to match the sacrificial layers, then lateral etching is minimized, but additional process steps are required
Solution Approach 1:
The intermediate structure is formed in advance with a thickness specifically designed to match the sacrificial layers. This preliminary action of controlling the intermediate structure thickness before the etching process ensures that when etching occurs, both the intermediate structure and sacrificial layers are removed at the same rate, minimizing lateral etching. Although this adds a process step, it simplifies subsequent etching operations by eliminating the need for complex lateral etching compensation.
Data Source
AI summary
A method for making a semiconductor device includes forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another. The method includes forming a dummy gate structure, over the fin structure, that extends along a second direction perpendicular to the first direction. The method includes forming a gate spacer extending along respective upper sidewall portions of the dummy gate structure, thereby defining a first distance between a bottom surface of the gate spacer and a top surface of a topmost one of the plurality of channel layers. The first distance is either zero or similar to a second distance that separates neighboring ones of the plurality of channel layers.