GAA Gate Spacer Insulation to Prevent Outer Gate Funnel Profile
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Solution Overview
Problem
Existing gate-all-around (GAA) transistors suffer from an undesired funnel profile of the outer gate structure, leading to decreased process window and increased leakage between the gate structure and contacts.
Innovation Solution
The formation of insulating layers on the sidewalls of the upper portions of the gate spacers during the removal of the dummy gate structure, which protects the gate spacers from subsequent manufacturing processes and maintains the critical dimension of the gate structure, thereby preventing a funnel profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the dummy gate structure is removed without protection, then the gate structure can be formed, but the gate spacer sidewalls develop a funnel profile leading to increased leakage and decreased process window
Solution Approach 1:
An insulating layer is formed on the sidewalls of the gate spacer upper portion before subsequent manufacturing processes. This preliminary protective action prevents the funnel profile from developing during later processing steps, maintaining straight sidewalls and preventing leakage without interfering with the final gate structure formation.
Solution Approach 2:
The insulating layer acts as an intermediary protective element between the gate spacer and the subsequent manufacturing processes. This intermediate layer shields the gate spacer sidewalls from processes that would otherwise cause funnel profile formation, while being removable or compatible with the final device structure.
2Ease of manufacture
If the gate spacer is exposed to subsequent manufacturing processes, then the gate structure can be formed, but the critical dimension control is degraded due to funnel profile formation
Solution Approach 1:
The insulating layer is deposited on the gate spacer sidewalls before contact formation processes. This preliminary protection maintains the critical dimensions of the gate structure throughout subsequent processing, ensuring precise control while enabling easier contact formation with an increased process window.
Solution Approach 2:
The insulating layer serves as a protective intermediary during contact formation, preventing direct interaction between subsequent processes and the gate spacer. This intermediary layer preserves critical dimension control while allowing manufacturing processes to proceed with greater ease and tolerance.
3Device complexity
If no protective layer is formed on gate spacer sidewalls, then the manufacturing process is simpler, but the gate structure develops funnel profile reducing process window
Solution Approach 1:
A single insulating layer deposition step is performed on the gate spacer sidewalls as a preliminary protective measure. This minimal additional complexity prevents funnel profile formation, thereby increasing the overall process window and making subsequent manufacturing easier despite the small increase in initial steps.
Solution Approach 2:
The insulating layer introduces a simple intermediary step that protects the gate spacer during manufacturing. This small increase in device complexity at the protective layer level yields a net gain in ease of manufacture by preventing funnel profile-related complications in later processing.
Data Source
AI summary
A method of forming a semiconductor structure, includes forming a fin structure over a substrate in a Z-direction; forming a dummy gate structure extending in a Y-direction and over the fin structure; and forming gate spacers on sidewalls of the dummy gate structure. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes removing a portion of the dummy gate structure to form a first trench that exposes upper portions of the gate spacers; forming an insulating material in the first trench; partially removing the insulating material to form insulating layers on sidewalls of the upper portions of the gate spacers; removing a remaining portion of the dummy gate structure to expose lower portions of the gate spacers; and partially etching the lower portions of the gate spacers.