GAA Gate Spacer Thickening for Source/Drain Isolation
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Solution Overview
Problem
Conventional gate-all-around (GAA) transistors face challenges in ensuring sufficient separation between the source/drain features and the gate structure, which can lead to electrical shorts and damage during the fabrication process.
Innovation Solution
The method involves selectively etching sacrificial layers before forming gate spacers, allowing the gate spacer layers to fill recesses and increase their thickness at the interface with the sacrificial layers. This thickened spacer design reduces the risk of etching through and minimizes electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate spacer layers are formed with uniform thickness, then the fabrication process is simple, but the protection to source/drain features is insufficient and electrical shorts may occur
Solution Approach 1:
The gate spacer structure is designed with non-uniform thickness, where the first gate spacer has a first thickness and the second gate spacer has a second thickness that is greater than the first thickness. This local variation in thickness provides enhanced protection to the source/drain features at critical locations while maintaining simplicity in other areas, thereby resolving the contradiction between reliability and device complexity.
2Reliability
If gate spacer thickness is increased to prevent electrical shorts, then protection to source/drain features is improved, but the fabrication process complexity increases
Solution Approach 1:
The method forms the first gate spacer before forming the second gate spacer. This preliminary action allows the thicker second gate spacer to be deposited over the existing first gate spacer, ensuring that the source/drain features are protected from the beginning of the process. This sequential approach prevents electrical shorts while maintaining ease of manufacture through a straightforward multi-step deposition process.
3Ease of manufacture
If uniform thickness gate spacers are used, then manufacturing is simpler, but electrical shorts between gate structure and source/drain features may occur
Solution Approach 1:
The gate spacer structure is designed with non-uniform thickness, where the first gate spacer has a first thickness and the second gate spacer has a second thickness that is greater than the first thickness. This local variation in thickness provides enhanced protection to the source/drain features at critical locations while maintaining simplicity in other areas, thereby resolving the contradiction between reliability and device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased thickness of the gate spacers provides enhanced protection for the source/drain features and reduces the likelihood of electrical shorts between the metal gate structure and the source/drain features, thereby improving the overall performance and reliability of the GAA transistors.
Implementation Method 1
performing a first etching process to selectively recess the second semiconductor layers
Implementation Method 2
forming a gate spacer layer over the dummy gate structure and the stack of semiconductor layers
Data Source
AI summary
A method includes providing a workpiece comprising a stack of semiconductor layers including interleaving first semiconductor layers and second semiconductor layers, forming a dummy gate structure to wrap over a channel region of the stack of semiconductor layers, performing a first etching process to selectively recess the second semiconductor layers, forming a gate spacer layer over the dummy gate structure and the stack of semiconductor layers, recessing a source/drain region of the stack of semiconductor layers to form a source/drain opening, performing a second etching process to selectively recess the second semiconductor layers from the source/drain opening to form inner spacer recesses, forming inner spacers in the inner spacer recesses, forming a source/drain feature in the source/drain opening, and replacing the dummy gate structure and the second semiconductor layers with a gate structure.