GAA Gate Structure With Tenon-Mortise Dielectric Spacer Protection
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Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) devices face challenges as they are not entirely satisfactory in all aspects, particularly in maintaining performance and integrity during scaling down processes.
Innovation Solution
The implementation of dielectric structures with tenon end portions and jog end portions in GAA transistors, which prevents over-etching and damage to gate spacers during the formation of the gate structure, enhancing the performance and reliability of GAA transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used for GAA devices, then existing technologies can be applied, but over-etching and damage to gate spacers occur during scaling down
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure with predetermined dimensions and positioning before the etching process. This mandrel serves as a pre-established reference that guides subsequent gate spacer formation, ensuring that the gate spacers are deposited at the correct location and thickness before any etching occurs, thereby preventing over-etching damage
Solution Approach 2:
The patent introduces a mandrel as an intermediary structure that mediates between the substrate and the gate spacers. This mandrel acts as a temporary placeholder and reference structure during the fabrication process, enabling precise positioning and protecting the gate spacer regions from over-etching, thus resolving the contradiction between manufacturing precision and device reliability
2Area of stationary object
If GAA devices are scaled down to reduce chip footprint, then chip area is reduced, but manufacturing challenges increase
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into distinct components: a mandrel structure, gate spacers, and channel regions. This segmentation allows each component to be formed and controlled independently, simplifying the manufacturing process despite the scaled-down dimensions, and enabling precise control over each element's geometry and position
Solution Approach 2:
The patent transitions from two-dimensional planar structures to three-dimensional vertically-stacked nanosheet channels with surrounding gate spacers. This dimensional change allows the device to achieve higher functionality and control in a smaller footprint by utilizing the vertical dimension, while the mandrel-based approach maintains manufacturing simplicity through systematic 3D structure formation
Data Source
AI summary
A semiconductor structure includes a substrate, nanostructures, source/drain features, a gate structure, and a dielectric structure. The nanostructures are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are electrically connected to and on opposite sides of the nanostructures in an X-direction. The gate structure extends in a Y-direction and wraps around the nanostructures. The gate structure includes a mortise end portion. The dielectric structure extends in the Y-direction and is in contact with the gate structure in the Y-direction. The dielectric structure includes a tenon end portion matching the mortise end portion of the gate structure.