GAA Gate Spacer Profile to Prevent Gate-to-Source Drain Shorts
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Solution Overview
Problem
Existing methods for forming non-planar transistor devices, such as GAA FETs, face issues with short circuits between the active gate structure and source/drain structures due to the remnants of the etch stop layer, leading to improper transistor function and performance limitations.
Innovation Solution
The etch stop layer is patterned before forming the gate spacer, creating a mesa-like profile that isolates the etch stop layer, preventing short circuits and allowing for a wider process window in forming the active gate structure, which wraps around the channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the etch stop layer is not patterned before forming the gate spacer, then the manufacturing process is simpler, but short circuits occur between the active gate structure and source/drain structures
Solution Approach 1:
The etch stop layer is patterned before forming the gate spacer, creating a mesa-like profile in advance. This preliminary action isolates the etch stop layer and prevents short circuits between the active gate structure and source/drain structures, resolving the reliability issue while maintaining a manageable process sequence.
2Reliability
If the etch stop layer is patterned before forming the gate spacer, then short circuits are prevented, but the manufacturing process becomes more complex
Solution Approach 1:
Pattern the etch stop layer before forming the gate spacer to create an isolated mesa-like profile. This preliminary patterning step ensures proper transistor function by preventing short circuits, and the isolation effect actually simplifies subsequent processing by defining clear boundaries for the active gate structure formation.
Data Source
AI summary
A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.