GAA Nanostructure Gate Stack Spacing to Reduce Parasitic Capacitance
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with parasitic capacitance and device performance.
Innovation Solution
The method involves forming a semiconductor device structure with a gate all around (GAA) transistor design, where nanostructures are patterned using photolithography and self-aligned processes, and spacers are used to create trenches for source/drain structures, followed by the removal of nanostructure portions to increase the distance between the gate stack and nanostructures, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (e.g., self-aligned double patterning, self-aligned quadruple patterning) where each step creates a portion of the final pattern. This segmentation allows complex nanoscale features to be formed through sequential simpler steps, managing fabrication complexity while achieving high functional density
Solution Approach 2:
Sacrificial nanostructures are formed in advance before the actual transistor structures. These preliminary sacrificial structures serve as templates that guide subsequent self-aligned patterning steps, enabling precise feature formation at reduced dimensions without increasing overall process complexity
2Productivity
If feature sizes decrease to increase functional density, then more devices fit per chip area, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
The patent transitions from planar transistor designs to three-dimensional structures such as nanosheet FETs and FinFETs. By stacking multiple thin semiconductor sheets or creating vertical fins, the effective channel area increases in the vertical dimension, maintaining high functional density while reducing parasitic capacitance through improved gate control and increased surface area for current flow
Solution Approach 2:
Multiple nanosheet layers are stacked vertically within a single device footprint, with each layer acting as an independent or interconnected transistor channel. This nested arrangement increases functional density by utilizing the vertical dimension while maintaining optimal spacing between layers to control parasitic effects and preserve device performance
3Productivity
If gate stack and nanostructure spacing is reduced to increase device density, then more devices fit in given area, but parasitic capacitance between gate and channel increases
Solution Approach 1:
The gate dielectric layer is engineered with spatially varying properties - using high-k dielectric materials in specific regions adjacent to the channel while maintaining thinner effective oxide thickness in other areas. This local quality variation allows reduced gate-to-channel spacing for higher device density while controlling parasitic capacitance through material selection and structural optimization at critical interfaces
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, a metal gate stack, and a spacer structure. The first nanostructure is between the second nanostructure and the substrate, the metal gate stack surrounds the first nanostructure and the second nanostructure, and the spacer structure surrounds an upper portion of the metal gate stack over the second nanostructure. The method includes removing the upper portion of the metal gate stack to form a first trench in the spacer structure. The method includes removing a first portion of the second nanostructure through the first trench after removing the upper portion of the metal gate stack.