GAA Gate Stacks With Split NFET/PFET Work Functions
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Solution Overview
Problem
The challenge of achieving ultra-low threshold voltages in field effect transistors (FETs) is constrained by the thickness of work function metal layers in gate stacks, which are limited by the geometry of nanostructured channel regions, particularly in gate-all-around (GAA) FETs, and existing methods are complex and costly.
Innovation Solution
The formation of FETs with different gate structures on a single substrate, including Al-based NFET and Al-free PFET gate stacks, utilizing n-type and p-type work function metal layers with selective deposition and metal growth inhibition layers to achieve ultra-low threshold voltages, allowing for thinner gate stack layers and reduced contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If work function metal layers are made thinner to achieve ultra-low threshold voltages, then threshold voltage control is improved, but manufacturing complexity and cost increase due to selective deposition requirements
Solution Approach 1:
The gate stack is segmented into distinct regions: Al-based NFET gate stacks with n-type work function metal layers for n-type FETs, and Al-free PFET gate stacks with p-type work function metal layers for p-type FETs. This segmentation allows each region to be optimized independently for its specific threshold voltage requirements without compromising the other device type.
Solution Approach 2:
Different work function metal layer compositions are applied locally to different device regions. NFET regions receive Al-based gate stacks with n-type work function metal layers, while PFET regions receive Al-free gate stacks with p-type work function metal layers. This local quality differentiation enables precise threshold voltage control tailored to each device type's electrical characteristics.
2Reliability
If work function metal layers are made thinner to reduce contamination, then device reliability is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The work function metal layer thickness is optimized to be in the range of 1 nm to 3 nm, which is thin enough to reduce contamination and achieve ultra-low threshold voltages, yet thick enough to maintain manufacturing precision and device reliability. This parameter optimization balances the competing requirements of reliability and precision.
Solution Approach 2:
Metal growth inhibition layers are introduced as intermediary elements between the work function metal layers and other gate stack components. These inhibition layers prevent unwanted metal deposition and contamination while allowing the thin work function metal layers to maintain their precise thickness and electrical properties.
3Manufacturing precision
If selective deposition and metal growth inhibition layers are used to achieve ultra-low threshold voltages, then threshold voltage tuning is improved, but device complexity increases
Solution Approach 1:
The gate stack structure is segmented into functionally distinct layers: work function metal layers for threshold voltage control, metal growth inhibition layers for contamination prevention, and gate dielectric layers for electrical isolation. This segmentation enables precise threshold voltage tuning while organizing complexity into manageable, functionally-defined components.
Solution Approach 2:
Metal growth inhibition layers are deposited preliminarily during the gate stack formation process, before subsequent metal deposition steps. This preliminary action prevents contamination of the thin work function metal layers during manufacturing, ensuring ultra-low threshold voltage performance without requiring complex post-processing corrections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the manufacturing of reliable FETs with smaller dimensions and ultra-low threshold voltages, reducing complexity and cost while maintaining performance, by using Al-based NFET and Al-free PFET gate stacks with selective deposition and inhibition layers.
Implementation Method 1
utilizing n-type and p-type work function metal layers with selective deposition
Implementation Method 2
metal growth inhibition layers to achieve ultra-low threshold voltages, allowing for thinner gate stack layers and reduced contamination
Data Source
AI summary
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.